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Message-ID: <CAEbi=3fsaDjX3iWLTLMHK-2PqvZ9XV3QnG4rz1wNa9-WQWyYZw@mail.gmail.com>
Date: Thu, 4 Jan 2018 15:57:36 +0800
From: Greentime Hu <green.hu@...il.com>
To: Rob Herring <robh+dt@...nel.org>
Cc: Greentime <greentime@...estech.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Arnd Bergmann <arnd@...db.de>,
linux-arch <linux-arch@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
netdev <netdev@...r.kernel.org>,
Vincent Chen <deanbo422@...il.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, Al Viro <viro@...iv.linux.org.uk>,
David Howells <dhowells@...hat.com>,
Will Deacon <will.deacon@....com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
linux-serial@...r.kernel.org,
Geert Uytterhoeven <geert.uytterhoeven@...il.com>,
Linus Walleij <linus.walleij@...aro.org>,
Mark Rutland <mark.rutland@....com>, Greg KH <greg@...ah.com>,
Guo Ren <ren_guo@...ky.com>,
Randy Dunlap <rdunlap@...radead.org>,
David Miller <davem@...emloft.net>,
Jonas Bonn <jonas@...thpole.se>,
Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>,
Stafford Horne <shorne@...il.com>,
Vincent Chen <vincentc@...estech.com>
Subject: Re: [PATCH v5 26/39] nds32: Device tree support
2018-01-04 3:14 GMT+08:00 Rob Herring <robh+dt@...nel.org>:
> On Tue, Jan 2, 2018 at 2:24 AM, Greentime Hu <green.hu@...il.com> wrote:
>> From: Greentime Hu <greentime@...estech.com>
>>
>> This patch adds support for device tree.
>>
>> Signed-off-by: Vincent Chen <vincentc@...estech.com>
>> Signed-off-by: Greentime Hu <greentime@...estech.com>
>> ---
>> arch/nds32/boot/dts/Makefile | 8 +++++
>> arch/nds32/boot/dts/ae3xx.dts | 73 +++++++++++++++++++++++++++++++++++++++++
>> arch/nds32/kernel/devtree.c | 19 +++++++++++
>> 3 files changed, 100 insertions(+)
>> create mode 100644 arch/nds32/boot/dts/Makefile
>> create mode 100644 arch/nds32/boot/dts/ae3xx.dts
>> create mode 100644 arch/nds32/kernel/devtree.c
>>
>> diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
>> new file mode 100644
>> index 0000000..d31faa8
>> --- /dev/null
>> +++ b/arch/nds32/boot/dts/Makefile
>> @@ -0,0 +1,8 @@
>> +ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
>> +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
>> +else
>> +BUILTIN_DTB :=
>> +endif
>> +obj-$(CONFIG_OF) += $(BUILTIN_DTB)
>> +
>> +clean-files := *.dtb *.dtb.S
>> diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
>> new file mode 100644
>> index 0000000..6b23d60
>> --- /dev/null
>> +++ b/arch/nds32/boot/dts/ae3xx.dts
>> @@ -0,0 +1,73 @@
>> +/dts-v1/;
>> +/ {
>> + compatible = "andestech,ae3xx";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + interrupt-parent = <&intc>;
>> +
>> + chosen {
>> + stdout-path = &serial0;
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x00000000 0x40000000>;
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu@0 {
>> + device_type = "cpu";
>> + compatible = "andestech,n13", "andestech,nds32v3";
>> + reg = <0>;
>> + clock-frequency = <60000000>;
>> + next-level-cache = <&L2>;
>> + };
>> + };
>> +
>> + L2: l2-cache@...00000 {
>> + compatible = "andestech,atl2c";
>> + reg = <0xe0500000 0x1000>;
>> + cache-unified;
>> + cache-level = <2>;
>> + };
>> +
>> + apb: clk@0 {
>
> unit address without reg is not valid. Drop the "@0".
>
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <30000000>;
>> + };
>> +
>> +
>> + intc: interrupt-controller {
>> + compatible = "andestech,ativic32";
>> + #interrupt-cells = <1>;
>> + interrupt-controller;
>> + };
>> +
>> + serial0: serial@...00000 {
>
> All the memory mapped peripherals should be under at least one simple-bus node.
>
>> + compatible = "andestech,uart16550", "ns16550a";
>> + reg = <0xf0300000 0x1000>;
>> + interrupts = <8>;
>> + clock-frequency = <14745600>;
>> + reg-shift = <2>;
>> + reg-offset = <32>;
>> + no-loopback-test = <1>;
>> + };
>> +
>> + timer0: timer@...00000 {
>> + compatible = "andestech,atcpit100";
>> + reg = <0xf0400000 0x1000>;
>> + interrupts = <2>;
>> + clocks = <&apb>;
>> + clock-names = "PCLK";
>> + };
>> +
>> + mac0: mac@...00000 {
>
> ethernet@...
>
Hi, Rob:
I'd like to modify it like this in the next version patch.
clock: clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <30000000>;
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
serial0: serial@...00000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0xf0300000 0x1000>;
interrupts = <8>;
clock-frequency = <14745600>;
reg-shift = <2>;
reg-offset = <32>;
no-loopback-test = <1>;
};
timer0: timer@...00000 {
compatible = "andestech,atcpit100";
reg = <0xf0400000 0x1000>;
interrupts = <2>;
clocks = <&clock>;
clock-names = "PCLK";
};
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
L2: cache-controller@...00000 {
compatible = "andestech,atl2c";
reg = <0xe0500000 0x1000>;
cache-unified;
cache-level = <2>;
};
mac0: ethernet@...00000 {
compatible = "andestech,atmac100";
reg = <0xe0100000 0x1000>;
interrupts = <18>;
};
};
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