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Message-Id: <1515032961-29131-5-git-send-email-hpeter+linux_kernel@gmail.com>
Date:   Thu,  4 Jan 2018 10:29:21 +0800
From:   "Ji-Ze Hong (Peter Hong)" <hpeter@...il.com>
To:     johan@...nel.org
Cc:     gregkh@...uxfoundation.org, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org, peter_hong@...tek.com.tw,
        "Ji-Ze Hong (Peter Hong)" <hpeter+linux_kernel@...il.com>
Subject: [PATCH V2 5/5] usb: serial: f81534: fix tx error on some baud rate

The F81532/534 had 4 clocksource 1.846/18.46/14.77/24MHz and baud rates
can be up to 1.5Mbits with 24MHz. But on some baud rate (384~500kps), the
TX side will send the data frame too close to treat frame error on RX
side. This patch will force all TX data frame with delay 1bit gap.

Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@...il.com>
---
V2:
	1: First introduced in this series patches.

 drivers/usb/serial/f81534.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/usb/serial/f81534.c b/drivers/usb/serial/f81534.c
index a4666171239a..513805eeae6a 100644
--- a/drivers/usb/serial/f81534.c
+++ b/drivers/usb/serial/f81534.c
@@ -130,6 +130,7 @@
 #define F81534_CLK_18_46_MHZ		(F81534_UART_EN | BIT(1))
 #define F81534_CLK_24_MHZ		(F81534_UART_EN | BIT(2))
 #define F81534_CLK_14_77_MHZ		(F81534_UART_EN | BIT(1) | BIT(2))
+#define F81534_CLK_TX_DELAY_1BIT	BIT(3)
 
 #define F81534_CLK_RS485_MODE		BIT(4)
 #define F81534_CLK_RS485_INVERT		BIT(5)
@@ -1438,6 +1439,11 @@ static int f81534_port_probe(struct usb_serial_port *port)
 		break;
 	}
 
+	/*
+	 * We'll make tx frame error when baud rate from 384~500kps. So we'll
+	 * delay all tx data frame with 1bit.
+	 */
+	port_priv->shadow_clk |= F81534_CLK_TX_DELAY_1BIT;
 	return f81534_set_port_output_pin(port);
 }
 
-- 
2.7.4

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