linux-kernel - Re: [PATCH 0/7] IBRS patch series

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Message-ID: <2b40f988-e773-97a5-77ca-de0908887ae2@redhat.com>
Date:   Fri, 5 Jan 2018 15:26:25 +0100
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     Greg KH <gregkh@...uxfoundation.org>,
        Yves-Alexis Perez <corsac@...ian.org>
Cc:     Henrique de Moraes Holschuh <hmh@...ian.org>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        Justin Forbes <jmforbes@...uxtx.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Andy Lutomirski <luto@...nel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Dave Hansen <dave.hansen@...el.com>,
        Andrea Arcangeli <aarcange@...hat.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Arjan Van De Ven <arjan.van.de.ven@...el.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/7] IBRS patch series

On 05/01/2018 15:01, Greg KH wrote:
>> Obviously it lacks a *lot* of processors (especially pre-Haswell).
> 
> I'm running Arch, but it would be nice to know where those microcode
> updates came from, given that they aren't on the "official" Intel page
> yet :)

Those from November seem way too early to include IBRS/IBPB.  Maybe the
two from December 3rd, but I wouldn't be 100% sure.

So it would be even nicer to know how those microcode updates were tested.

(And by the way, the LFENCE change is for variant 1 aka CVE-2017-5753).

Paolo