linux-kernel - Re: [PATCH 0/7] IBRS patch series

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Message-ID: <1515164061.3305.17.camel@debian.org>
Date:   Fri, 05 Jan 2018 15:54:21 +0100
From:   Yves-Alexis Perez <corsac@...ian.org>
To:     Paolo Bonzini <pbonzini@...hat.com>,
        Greg KH <gregkh@...uxfoundation.org>
Cc:     Henrique de Moraes Holschuh <hmh@...ian.org>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        Justin Forbes <jmforbes@...uxtx.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Andy Lutomirski <luto@...nel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Dave Hansen <dave.hansen@...el.com>,
        Andrea Arcangeli <aarcange@...hat.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Arjan Van De Ven <arjan.van.de.ven@...el.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/7] IBRS patch series

On Fri, 2018-01-05 at 15:26 +0100, Paolo Bonzini wrote:
> Those from November seem way too early to include IBRS/IBPB.  Maybe the
> two from December 3rd, but I wouldn't be 100% sure.

So, for my CPU with updated microcode:

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 61
model name	: Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz
stepping	: 4
microcode	: 0x28

cpuid returns:

   0x00000007 0x00: eax=0x00000000 ebx=0x021c27ab ecx=0x00000000
edx=0x0c000000

So bit 26/27 are set, which as I understand means IBRS is supported (but I
would appreciate any pointer to relevant documentation on this).
> 
> So it would be even nicer to know how those microcode updates were tested.

At least I didn't test IBRS/IBPB here. I could do it provided I'm pointed to a
tree with all the things to test.
> 
> (And by the way, the LFENCE change is for variant 1 aka CVE-2017-5753).

Ok, good to know. Is the kernel support part for LFENCE in the same thread (I
have to admit I'm a bit lost).

Regards,
-- 
Yves-Alexis
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