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Message-ID: <CALMp9eTqjn=uA=mw0y=2_3WROCnvAG3=ScG1bKu7qRhUwe5MQw@mail.gmail.com>
Date: Mon, 8 Jan 2018 10:52:46 -0800
From: Jim Mattson <jmattson@...gle.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>,
LKML <linux-kernel@...r.kernel.org>,
kvm list <kvm@...r.kernel.org>, aliguori@...zon.com,
Tom Lendacky <thomas.lendacky@....com>, dwmw@...zon.co.uk,
bp@...en8.de
Subject: Re: [PATCH 2/7] x86/msr: add definitions for indirect branch
predictor MSRs
I don't really understand the organization of this file, but I put
these MSRs in the /* Intel defined MSRs. */ block, between
MSR_IA32_TSC_ADJUST and MSR_IA32_BNDCFGS.
On Mon, Jan 8, 2018 at 10:35 AM, Konrad Rzeszutek Wilk
<konrad.wilk@...cle.com> wrote:
> On Mon, Jan 08, 2018 at 07:08:40PM +0100, Paolo Bonzini wrote:
>> KVM will start using them soon.
>
> Perhaps include a bit of description?
>>
>> Signed-off-by: Paolo Bonzini <pbonzini@...hat.com>
>> ---
>> arch/x86/include/asm/msr-index.h | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index 03ffde6217d0..ec08f1d8d39b 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -39,6 +39,11 @@
>>
>> /* Intel MSRs. Some also available on other CPUs */
>>
>> +#define MSR_IA32_SPEC_CTRL 0x00000048
>> +
>> +#define MSR_IA32_PRED_CMD 0x00000049
>> +#define FEATURE_SET_IBPB (1UL << 0)
>> +
>> #define MSR_PPIN_CTL 0x0000004e
>> #define MSR_PPIN 0x0000004f
>>
>> --
>> 1.8.3.1
>>
>>
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