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Message-ID: <20180110161656.hftp6lsnut7u6klr@linux.intel.com>
Date: Wed, 10 Jan 2018 18:16:56 +0200
From: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>
To: greg@...ellic.com
Cc: Pavel Machek <pavel@....cz>, platform-driver-x86@...r.kernel.org,
x86@...nel.org, linux-kernel@...r.kernel.org,
Borislav Petkov <bp@...e.de>,
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Haim Cohen <haim.cohen@...el.com>,
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Janakarajan Natarajan <Janakarajan.Natarajan@....com>,
Jim Mattson <jmattson@...gle.com>,
Kan Liang <Kan.liang@...el.com>,
"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Kyle Huey <me@...ehuey.com>, Len Brown <len.brown@...el.com>,
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<linux-fsdevel@...r.kernel.org>,
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Subject: Re: [PATCH v6 00/11] Intel SGX Driver
On Tue, Jan 09, 2018 at 03:50:23PM -0600, Dr. Greg Wettstein wrote:
> > Everything going out of L1 gets encrypted. This is done to defend
> > against peripheral like adversaries and should work also against
> > meltdown.
>
> I don't believe this is an architecturally correct assertion. The
> encryption/decryption occurs at the 'bottom' of the cache heirarchy.
You are right and I was wrong. It is plain from L1 to LLC, which implies
as you correctly described potential cache missing attacks in addition
to timing attacks.
/Jarkko
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