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Message-ID: <20180111222304.js3c3vrx3u5j3hvj@rob-hp-laptop>
Date: Thu, 11 Jan 2018 16:23:04 -0600
From: Rob Herring <robh@...nel.org>
To: Vivek Gautam <vivek.gautam@...eaurora.org>
Cc: joro@...tes.org, mark.rutland@....com, rjw@...ysocki.net,
gregkh@...uxfoundation.org, robdclark@...il.com,
will.deacon@....com, robin.murphy@....com, sboyd@...eaurora.org,
iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
len.brown@...el.com, pavel@....cz, airlied@...ux.ie,
sricharan@...eaurora.org, m.szyprowski@...sung.com,
architt@...eaurora.org, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v5 5/6] iommu/arm-smmu: Add support for qcom,smmu-v2
variant
On Tue, Jan 09, 2018 at 03:31:48PM +0530, Vivek Gautam wrote:
> qcom,smmu-v2 is an arm,smmu-v2 implementation with specific
> clock and power requirements. This smmu core is used with
> multiple masters on msm8996, viz. mdss, video, etc.
> Add bindings for the same.
>
> Signed-off-by: Vivek Gautam <vivek.gautam@...eaurora.org>
> ---
>
> * Major change in this patch -
> Changed compatible string from 'qcom,msm8996-smmu-v2' to
> 'qcom,smmu-v2' to reflect the IP version rather than the
> platform on which it is used.
The bugs and how things are connected are all the same? I'd suggest you
keep both strings.
> The same IP is used across multiple platforms including msm8996,
> and sdm845 etc.
But for only 2 or so platforms a fallback is not really worth it. You'll
probably be on SMMUv3 before too long...
>
> .../devicetree/bindings/iommu/arm,smmu.txt | 35 ++++++++++++++++++++++
> drivers/iommu/arm-smmu.c | 13 ++++++++
> 2 files changed, 48 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 8a6ffce12af5..e4951288c87c 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -17,6 +17,7 @@ conditions.
> "arm,mmu-401"
> "arm,mmu-500"
> "cavium,smmu-v2"
> + "qcom,smmu-v2"
>
> depending on the particular implementation and/or the
> version of the architecture implemented.
> @@ -71,6 +72,23 @@ conditions.
> or using stream matching with #iommu-cells = <2>, and
> may be ignored if present in such cases.
>
> +- clock-names: Should be "bus", and "iface" for "qcom,smmu-v2"
> + implementation.
> +
> + "bus" clock for "qcom,smmu-v2" is required for downstream
> + bus access and for the smmu ptw.
> +
> + "iface" clock is required to access smmu's registers through
> + the TCU's programming interface.
> +
> +- clocks: Phandles for respective clocks described by clock-names.
> +
> +- power-domains: Phandles to SMMU's power domain specifier. This is
> + required even if SMMU belongs to the master's power
> + domain, as the SMMU will have to be enabled and
> + accessed before master gets enabled and linked to its
> + SMMU.
> +
> ** Deprecated properties:
>
> - mmu-masters (deprecated in favour of the generic "iommus" binding) :
> @@ -137,3 +155,20 @@ conditions.
> iommu-map = <0 &smmu3 0 0x400>;
> ...
> };
> +
> + /* Qcom's arm,smmu-v2 implementation */
> + smmu4: iommu {
> + compatible = "qcom,smmu-v2";
> + reg = <0xd00000 0x10000>;
> +
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> + #iommu-cells = <1>;
> + power-domains = <&mmcc MDSS_GDSC>;
> +
> + clocks = <&mmcc SMMU_MDP_AXI_CLK>,
> + <&mmcc SMMU_MDP_AHB_CLK>;
> + clock-names = "bus", "iface";
> + };
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 33bbcfedb896..2ade214c41bc 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -119,6 +119,7 @@ enum arm_smmu_implementation {
> GENERIC_SMMU,
> ARM_MMU500,
> CAVIUM_SMMUV2,
> + QCOM_SMMUV2,
> };
>
> struct arm_smmu_s2cr {
> @@ -1971,6 +1972,17 @@ struct arm_smmu_match_data {
> ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
> ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
>
> +static const char * const qcom_smmuv2_clks[] = {
> + "bus", "iface",
> +};
> +
> +static const struct arm_smmu_match_data qcom_smmuv2 = {
> + .version = ARM_SMMU_V2,
> + .model = QCOM_SMMUV2,
> + .clks = qcom_smmuv2_clks,
> + .num_clks = ARRAY_SIZE(qcom_smmuv2_clks),
> +};
> +
> static const struct of_device_id arm_smmu_of_match[] = {
> { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
> { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
> @@ -1978,6 +1990,7 @@ struct arm_smmu_match_data {
> { .compatible = "arm,mmu-401", .data = &arm_mmu401 },
> { .compatible = "arm,mmu-500", .data = &arm_mmu500 },
> { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
> + { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
> { },
> };
> MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
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