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Message-ID: <CAFp+6iEOAYBs9iLZk9=dCCJ6WLuToJGcbo1+MFu3mkuFYBBY7Q@mail.gmail.com>
Date: Fri, 12 Jan 2018 11:56:02 +0530
From: Vivek Gautam <vivek.gautam@...eaurora.org>
To: Manu Gautam <mgautam@...eaurora.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Felipe Balbi <balbi@...nel.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
Linux USB Mailing List <linux-usb@...r.kernel.org>,
Varadarajan Narayanan <varada@...eaurora.org>,
smuthayy <smuthayy@...eaurora.org>,
Wei Yongjun <weiyongjun1@...wei.com>,
Fengguang Wu <fengguang.wu@...el.com>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 10/16] phy: qcom-qmp: Move register offsets to header file
Hi Manu,
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam <mgautam@...eaurora.org> wrote:
> New revision (v3) of QMP PHY uses different offsets
> for almost all of the registers. Hence, move these
> definitions to header file so that updated offsets
> can be added for QMP v3.
>
> Signed-off-by: Manu Gautam <mgautam@...eaurora.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 119 +------------------------------
> drivers/phy/qualcomm/phy-qcom-qmp.h | 137 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 138 insertions(+), 118 deletions(-)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp.h
>
[snip]
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> new file mode 100644
> index 0000000..d930ca7
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -0,0 +1,137 @@
> +/*
> + * Copyright (c) 2017, Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
nit: "SPDX-License" identifier now? That's less number of lines too :)
And when you are doing that, can you please consider moving
phy-qcom-qmp and phy-qcom-qusb2 as well to the new SPDX license
identifier. That will be cleaner.
Thanks!
> +
> +#ifndef QCOM_PHY_QMP_H_
> +#define QCOM_PHY_QMP_H_
> +
> +/* Only for QMP V2 PHY - QSERDES COM registers */
> +#define QSERDES_COM_BG_TIMER 0x00c
> +#define QSERDES_COM_SSC_EN_CENTER 0x010
> +#define QSERDES_COM_SSC_ADJ_PER1 0x014
> +#define QSERDES_COM_SSC_ADJ_PER2 0x018
> +#define QSERDES_COM_SSC_PER1 0x01c
> +#define QSERDES_COM_SSC_PER2 0x020
> +#define QSERDES_COM_SSC_STEP_SIZE1 0x024
> +#define QSERDES_COM_SSC_STEP_SIZE2 0x028
> +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
> +#define QSERDES_COM_CLK_ENABLE1 0x038
> +#define QSERDES_COM_SYS_CLK_CTRL 0x03c
> +#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
> +#define QSERDES_COM_PLL_IVCO 0x048
> +#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
> +#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
> +#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
> +#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
> +#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
> +#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
> +#define QSERDES_COM_BG_TRIM 0x070
> +#define QSERDES_COM_CLK_EP_DIV 0x074
> +#define QSERDES_COM_CP_CTRL_MODE0 0x078
> +#define QSERDES_COM_CP_CTRL_MODE1 0x07c
> +#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
> +#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
> +#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
> +#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
> +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
> +#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
> +#define QSERDES_COM_RESETSM_CNTRL 0x0b4
> +#define QSERDES_COM_RESTRIM_CTRL 0x0bc
> +#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
> +#define QSERDES_COM_LOCK_CMP_EN 0x0c8
> +#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
> +#define QSERDES_COM_DEC_START_MODE0 0x0d0
> +#define QSERDES_COM_DEC_START_MODE1 0x0d4
> +#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
> +#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
> +#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
> +#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
> +#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
> +#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
> +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
> +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
> +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
> +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
> +#define QSERDES_COM_VCO_TUNE_CTRL 0x124
> +#define QSERDES_COM_VCO_TUNE_MAP 0x128
> +#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
> +#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
> +#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
> +#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
> +#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
> +#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
> +#define QSERDES_COM_BG_CTRL 0x170
> +#define QSERDES_COM_CLK_SELECT 0x174
> +#define QSERDES_COM_HSCLK_SEL 0x178
> +#define QSERDES_COM_CORECLK_DIV 0x184
> +#define QSERDES_COM_CORE_CLK_EN 0x18c
> +#define QSERDES_COM_C_READY_STATUS 0x190
> +#define QSERDES_COM_CMN_CONFIG 0x194
> +#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
> +#define QSERDES_COM_DEBUG_BUS0 0x1a0
> +#define QSERDES_COM_DEBUG_BUS1 0x1a4
> +#define QSERDES_COM_DEBUG_BUS2 0x1a8
> +#define QSERDES_COM_DEBUG_BUS3 0x1ac
> +#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
> +#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
> +
> +/* Only for QMP V2 PHY - TX registers */
> +#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
> +#define QSERDES_TX_DEBUG_BUS_SEL 0x064
> +#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
> +#define QSERDES_TX_LANE_MODE 0x094
> +#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
> +
> +/* Only for QMP V2 PHY - RX registers */
> +#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
> +#define QSERDES_RX_UCDR_SO_GAIN 0x01c
> +#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
> +#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
> +#define QSERDES_RX_RX_TERM_BW 0x090
> +#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
> +#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
> +#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
> +#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
> +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
> +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
> +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
> +#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
> +#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
> +#define QSERDES_RX_SIGDET_ENABLES 0x110
> +#define QSERDES_RX_SIGDET_CNTRL 0x114
> +#define QSERDES_RX_SIGDET_LVL 0x118
> +#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
> +#define QSERDES_RX_RX_BAND 0x120
> +#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
> +
> +/* Only for QMP V2 PHY - PCS registers */
> +#define QPHY_POWER_DOWN_CONTROL 0x04
> +#define QPHY_TXDEEMPH_M6DB_V0 0x24
> +#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
> +#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
> +#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
> +#define QPHY_POWER_STATE_CONFIG1 0x60
> +#define QPHY_POWER_STATE_CONFIG2 0x64
> +#define QPHY_POWER_STATE_CONFIG4 0x6c
> +#define QPHY_LOCK_DETECT_CONFIG1 0x80
> +#define QPHY_LOCK_DETECT_CONFIG2 0x84
> +#define QPHY_LOCK_DETECT_CONFIG3 0x88
> +#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
> +#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
> +#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
> +#define QPHY_OSC_DTCT_ACTIONS 0x1AC
> +#define QPHY_RX_SIGDET_LVL 0x1D8
> +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
> +#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
> +
> +#endif
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
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