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Message-ID: <1515760769.22302.445.camel@amazon.co.uk>
Date: Fri, 12 Jan 2018 12:39:29 +0000
From: "Woodhouse, David" <dwmw@...zon.co.uk>
To: Borislav Petkov <bp@...en8.de>, Ashok Raj <ashok.raj@...el.com>
CC: <linux-kernel@...r.kernel.org>,
Thomas Gleixner <tglx@...utronix.de>,
"Tim Chen" <tim.c.chen@...ux.intel.com>,
Andy Lutomirski <luto@...nel.org>,
"Linus Torvalds" <torvalds@...ux-foundation.org>,
Greg KH <gregkh@...uxfoundation.org>,
Dave Hansen <dave.hansen@...el.com>,
"Andrea Arcangeli" <aarcange@...hat.com>,
Andi Kleen <ak@...ux.intel.com>,
"Arjan Van De Ven" <arjan.van.de.ven@...el.com>,
Peter Zijlstra <peterz@...radead.org>,
Dan Williams <dan.j.williams@...el.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Jun Nakajima <jun.nakajima@...el.com>,
Asit Mallick <asit.k.mallick@...el.com>
Subject: Re: [PATCH 5/5] x86/feature: Detect the x86 feature Indirect
Branch Prediction Barrier
On Fri, 2018-01-12 at 13:32 +0100, Borislav Petkov wrote:
> On Thu, Jan 11, 2018 at 05:32:19PM -0800, Ashok Raj wrote:
> > cpuid ax=0x7, return rdx bit 26 to indicate presence of both
> > IA32_SPEC_CTRL(MSR 0x48) and IA32_PRED_CMD(MSR 0x49)
>
> So why do we need two X86_FEATURE flags then?
AMD has only the latter and enumerates them differently.
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