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Date:   Fri, 12 Jan 2018 18:23:07 +0000
From:   David Woodhouse <dwmw2@...radead.org>
To:     Andi Kleen <ak@...ux.intel.com>
Cc:     Paul Turner <pjt@...gle.com>, LKML <linux-kernel@...r.kernel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Greg Kroah-Hartman <gregkh@...ux-foundation.org>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        Dave Hansen <dave.hansen@...el.com>, tglx@...utronix.de,
        Kees Cook <keescook@...gle.com>,
        Rik van Riel <riel@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Andy Lutomirski <luto@...capital.net>,
        Jiri Kosina <jikos@...nel.org>, gnomes@...rguk.ukuu.org.uk,
        x86@...nel.org, thomas.lendacky@....com,
        Josh Poimboeuf <jpoimboe@...hat.com>
Subject: Re: [PATCH] x86/retpoline: Fill RSB on context switch for affected
 CPUs

On Fri, 2018-01-12 at 10:02 -0800, Andi Kleen wrote:
> > +     if ((!boot_cpu_has(X86_FEATURE_PTI) &&
> > +          !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
> > +             setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
> > +             pr_info("Filling RSB on context switch\n");
> 
> We need to do more things for Skylake (like idle and interrupt fill
> and possibly deep call cahin), so I don't think it makes sense to
> 
> - have an individual flag for each of these. It can be just a single
> flag that enables all of this for Skylake
> 
> - print something for each of them. that will just be very noisy
> without any useful benefit to the user.

I still think we are better off using IBRS by default on Skylake.

This patch wasn't really for Skylake; the real use case was for AMD
CPUs (!PTI) without SMEP. Since it happens to needed on Skylake too we
might as well enable it there... but that doesn't mean I was planning
to do all the other horrible crap we need for Skylake.
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