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Message-ID: <CACRpkdb3iS7FuGbC3n9xpazvtEW7AjbLKNZ5vKpJAv2D8c4sbA@mail.gmail.com>
Date: Mon, 15 Jan 2018 02:01:36 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Patrice CHOTARD <patrice.chotard@...com>
Cc: Russell King <linux@...linux.org.uk>,
Ulf Hansson <ulf.hansson@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexandre Torgue <alexandre.torgue@...com>,
linux-mmc <linux-mmc@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-clk <linux-clk@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-gpio@...r.kernel.org,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Andrea Merello <andrea.merello@...il.com>
Subject: Re: [PATCH 01/14] mmc: mmci: Don't pretend all variants to have
MMCIMASK1 register
On Fri, Jan 12, 2018 at 1:15 PM, <patrice.chotard@...com> wrote:
> From: Patrice Chotard <patrice.chotard@...com>
>
> Two mask registers are used in order to select which events have to
> actually generate an interrupt on each IRQ line.
>
> It seems that in the single-IRQ case it's assumed that the IRQs lines
> are simply OR-ed, while the two mask registers are still present. The
> driver still programs the two mask registers separately.
>
> However the STM32 variant has only one IRQ, and also has only one mask
> register.
>
> This patch prepares for STM32 variant support by making the driver using
> only one mask register.
>
> This patch also optimize the MMCIMASK1 mask usage by caching it into
> host->mask1_reg which avoid to read it into mmci_irq().
>
> Tested only on STM32 variant. RFT for variants other than STM32
>
> Signed-off-by: Andrea Merello <andrea.merello@...il.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@...com>
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>
Yours,
Linus Walleij
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