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Message-ID: <20180117021346.GA26166@Asurada-Nvidia>
Date:   Tue, 16 Jan 2018 18:13:48 -0800
From:   Nicolin Chen <nicoleotsuka@...il.com>
To:     Marc Zyngier <marc.zyngier@....com>
Cc:     mark.rutland@....com, catalin.marinas@....com, will.deacon@....com,
        oleg@...hat.com, cdall@...aro.org, tbaicar@...eaurora.org,
        julien.thierry@....com, Dave.Martin@....com, robin.murphy@....com,
        james.morse@....com, ard.biesheuvel@...aro.org,
        xiexiuqi@...wei.com, mingo@...nel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC v1] arm64: Handle traps from accessing CNTVCT/CNTFRQ
 for CONFIG_COMPAT

On Tue, Jan 16, 2018 at 01:37:46PM -0800, Nicolin Chen wrote:
> On Tue, Jan 16, 2018 at 09:19:13PM +0000, Marc Zyngier wrote:
> 
> > > I understand that it should take care of the condition field as
> > > a general instruction handler. Just for curiosity: If we confine
> > > the topic to read access of CNTVCT/CNTFRQ, what'd be the penalty
> > > by ignoring the condition field and executing it anyway?
> > 
> > Do you mean, apart from severely corrupting userspace execution?
> > That's a rhetorical question, right?
> 
> I don't quite understand the corrupting userspace execution part.
> What I see for a conditional CNTVCT read is more likely:
> 	if (condition) {	// in this case, if (true)
> 		r1 = lower32(cntvct);
> 		r2 = higher32(cntvct);
> 	}
> 
> Could you please elaborate a bit? Thank you.

I guess I got it now. The concern seems to be Thumb instructions.
So ignoring a condition for a Thumb instruction may cause its IT
scope shifting. For ARM mode, the only penalty could be two Rts
getting written -- which shouldn't corrupt userspace execution.

Please correct me if I am wrong or not thorough.

Thanks
Nicolin

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