linux-kernel - [tip:x86/cache] x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 18 Jan 2018 00:37:57 -0800
From:   tip-bot for Fenghua Yu <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     vikas.shivappa@...el.com, mingo@...nel.org, tglx@...utronix.de,
        tony.luck@...el.com, ravi.v.shankar@...el.com,
        fenghua.yu@...el.com, reinette.chatre@...el.com,
        linux-kernel@...r.kernel.org, hpa@...or.com,
        sai.praneeth.prakhya@...el.com
Subject: [tip:x86/cache] x86/intel_rdt: Enumerate L2 Code and Data
 Prioritization (CDP) feature

Commit-ID:  a511e7935378ef1f321456a90beae2a2632d3d83
Gitweb:     https://git.kernel.org/tip/a511e7935378ef1f321456a90beae2a2632d3d83
Author:     Fenghua Yu <fenghua.yu@...el.com>
AuthorDate: Wed, 20 Dec 2017 14:57:21 -0800
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Thu, 18 Jan 2018 09:33:30 +0100

x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature

L2 Code and Data Prioritization (CDP) is enumerated in
CPUID(EAX=0x10, ECX=0x2):ECX.bit2

Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: "Ravi V Shankar" <ravi.v.shankar@...el.com>
Cc: "Tony Luck" <tony.luck@...el.com>
Cc: Vikas" <vikas.shivappa@...el.com>
Cc: Sai Praneeth" <sai.praneeth.prakhya@...el.com>
Cc: Reinette" <reinette.chatre@...el.com>
Link: https://lkml.kernel.org/r/1513810644-78015-4-git-send-email-fenghua.yu@intel.com


---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kernel/cpu/scattered.c    | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 25b9375..67bbfaa 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -206,6 +206,7 @@
 #define X86_FEATURE_RETPOLINE		( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
 #define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
 #define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */
+#define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */
 #define X86_FEATURE_AVX512_4VNNIW	( 7*32+16) /* AVX-512 Neural Network Instructions */
 #define X86_FEATURE_AVX512_4FMAPS	( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
 
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index d0e6976..df4d8f7 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -26,6 +26,7 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_CAT_L3,		CPUID_EBX,  1, 0x00000010, 0 },
 	{ X86_FEATURE_CAT_L2,		CPUID_EBX,  2, 0x00000010, 0 },
 	{ X86_FEATURE_CDP_L3,		CPUID_ECX,  2, 0x00000010, 1 },
+	{ X86_FEATURE_CDP_L2,		CPUID_ECX,  2, 0x00000010, 2 },
 	{ X86_FEATURE_MBA,		CPUID_EBX,  3, 0x00000010, 0 },
 	{ X86_FEATURE_HW_PSTATE,	CPUID_EDX,  7, 0x80000007, 0 },
 	{ X86_FEATURE_CPB,		CPUID_EDX,  9, 0x80000007, 0 },