lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <alpine.DEB.2.20.1801181004000.1847@nanos>
Date:   Thu, 18 Jan 2018 10:06:14 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Keith Busch <keith.busch@...el.com>
cc:     LKML <linux-kernel@...r.kernel.org>
Subject: Re: [BUG 4.15-rc7] IRQ matrix management errors

On Thu, 18 Jan 2018, Keith Busch wrote:

> On Thu, Jan 18, 2018 at 09:10:43AM +0100, Thomas Gleixner wrote:
> > Can you please provide the output of
> > 
> > # cat /sys/kernel/debug/irq/irqs/$ONE_I40_IRQ
> 
> # cat /sys/kernel/debug/irq/irqs/48
> handler:  handle_edge_irq
> device:   0000:1a:00.0
> status:   0x00000000
> istate:   0x00000000
> ddepth:   0
> wdepth:   0
> dstate:   0x05401200
>             IRQD_ACTIVATED
>             IRQD_IRQ_STARTED
>             IRQD_SINGLE_TARGET
>             IRQD_AFFINITY_SET
>             IRQD_CAN_RESERVE
> node:     0
> affinity: 0-27,56-83
> effectiv: 0
> pending:
> domain:  PCI-MSI-2
>  hwirq:   0xd00002
>  chip:    PCI-MSI
>   flags:   0x10
>              IRQCHIP_SKIP_SET_WAKE

Bah. That's MSI where we can't use interrupt reservation because we cant
mask MSI vectors. I really admire these designed by committee hardware
bogosities.

Thanks,

	tglx

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ