linux-kernel - Re: [PATCH v3 01/12] clk: sunxi-ng: Mask nkmp factors when setting register

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Message-ID: <20180118105323.fk65vo42eyc6dbzz@flea.lan>
Date:   Thu, 18 Jan 2018 11:53:23 +0100
From:   Maxime Ripard <maxime.ripard@...e-electrons.com>
To:     Jernej Skrabec <jernej.skrabec@...l.net>
Cc:     airlied@...ux.ie, robh+dt@...nel.org, mark.rutland@....com,
        wens@...e.org, architt@...eaurora.org, a.hajda@...sung.com,
        Laurent.pinchart@...asonboard.com, mturquette@...libre.com,
        sboyd@...eaurora.org, Jose.Abreu@...opsys.com,
        narmstrong@...libre.com, dri-devel@...ts.freedesktop.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [PATCH v3 01/12] clk: sunxi-ng: Mask nkmp factors when setting
 register

On Wed, Jan 17, 2018 at 09:14:10PM +0100, Jernej Skrabec wrote:
> Currently, if one of the factors isn't present, bit 0 gets always set to
> 1. For example, A83T has NMP PLLs modelled as NKMP PLL without K. Since
> K is not specified, it's offset, width and shift is 0. Driver assumes
> that lowest value possible is 1, otherwise we would get division by 0.
> That situation causes that bit 0 is always set, which may change wanted
> clock rate.
> 
> Fix that by masking every factor according to it's specified width.
> Factors with width set to 0 won't have any influence to final register
> value.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net>

Acked-by: Maxime Ripard <maxime.ripard@...e-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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