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Message-ID: <3908561D78D1C84285E8C5FCA982C28F7B3446FC@ORSMSX110.amr.corp.intel.com>
Date: Thu, 18 Jan 2018 17:26:15 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: "Kirill A. Shutemov" <kirill@...temov.name>,
Andrea Arcangeli <aarcange@...hat.com>
CC: Dave Hansen <dave.hansen@...ux.intel.com>,
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Subject: RE: [mm 4.15-rc8] Random oopses under memory pressure.
> Both are real page. But why do you expect pages to be 64-byte alinged?
> Both are aligned to 64-bit as they suppose to be IIUC.
On a 64-bit kernel sizeof struct page == 64 (after much work by people to
trim out excess stuff). So I thought we made sure to align the base address
of blocks of "struct page" so that every one neatly fits into one cache line.
-Tony
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