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Message-ID: <20180120142627.jttjdsenwsedvle6@gmail.com>
Date: Sat, 20 Jan 2018 15:26:27 +0100
From: Ingo Molnar <mingo@...nel.org>
To: Nadav Amit <nadav.amit@...il.com>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>,
LKML <linux-kernel@...r.kernel.org>,
Andy Lutomirski <luto@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>,
the arch/x86 maintainers <x86@...nel.org>, w@....eu,
Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [RFC] x86: Avoid CR3 load on compatibility mode with PTI
* Nadav Amit <nadav.amit@...il.com> wrote:
> > So we are trading a 5-15% slowdown (PTI) for another 5-15% slowdown, plus we
> > are losing the soft-SMEP feature on older CPUs that PTI enables, which is a
> > pretty powerful mitigation technique.
>
> This soft-SMEP can be kept by keeping PTI if SMEP is unsupported. Although we
> trade slowdowns, they are different ones, which allows the user to make his best
> decision.
Indeed, not allowing PTI to be disabled if SMEP is unavailable might be a
solution.
> > Yes, I suspect in some (maybe many) cases it would be a speedup, but I really
> > don't like the underlying assumptions and tradeoffs here. (Not that I like any
> > of this whole Meltdown debacle TBH.)
>
> To make sure that I understand correctly - the assumptions are that disabling
> PTI on compatibility mode would: (1) Benefit some workloads; (2) Be useful, even
> if we only consider CPUs with SMEP; and (3) Secure.
>
> Under these assumptions, the tradeoff is slightly greater code complexity for
> considerably better performance of 32-bit code; in some common cases this makes
> 32-bit code to perform significantly better than 64-bit code.
>
> Am I missing something? My main concern was initially security, but so far from
> your aggregated feedback I did not see something concrete which cannot
> relatively easily be addressed.
Yes, I suppose.
Thanks,
Ingo
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