lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 20 Jan 2018 21:57:00 +0000
From:   David Woodhouse <dwmw2@...radead.org>
To:     Steven Noonan <steven@...inklabs.net>
Cc:     Arjan van de Ven <arjan@...ux.intel.com>,
        Thomas Gleixner <tglx@...utronix.de>, karahmed@...zon.de,
        Linux-X86 <x86@...nel.org>,
        Linux Kernel mailing List <linux-kernel@...r.kernel.org>,
        tim.c.chen@...ux.intel.com, Borislav Petkov <bp@...en8.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Paolo Bonzini <pbonzini@...hat.com>, ak@...ux.intel.com,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        gregkh@...ux-foundation.org
Subject: Re: [PATCH 1/4] x86/cpufeatures: Add Intel feature bits for
 Speculation Control

On Sat, 2018-01-20 at 13:51 -0800, Steven Noonan wrote:
> 
> > +#define X86_FEATURE_STIPB              (18*32+27) /* Speculation
> Control with STIPB (Intel) */
> 
> Is this correct? I thought the acronym was "STIBP", i.e.
> "Single-Thread Indrect Branch Prediction"? If so, then you've got the
> B and P swapped.

Likewise in the later MSR bits patch where I actually have both 'STIPB'
and 'Single Thread Indirect Branch Predictors' on the *same* line.

Fixed in both now; thanks.
Download attachment "smime.p7s" of type "application/x-pkcs7-signature" (5213 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ