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Message-ID: <4e01a7a9-29e4-adcc-3f53-550fb7f3d370@amd.com>
Date: Tue, 23 Jan 2018 10:12:48 -0600
From: Tom Lendacky <thomas.lendacky@....com>
To: Andy Lutomirski <luto@...capital.net>,
KarimAllah Ahmed <karahmed@...zon.de>
Cc: linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>,
Andrea Arcangeli <aarcange@...hat.com>,
Andy Lutomirski <luto@...nel.org>,
Arjan van de Ven <arjan@...ux.intel.com>,
Ashok Raj <ashok.raj@...el.com>,
Asit Mallick <asit.k.mallick@...el.com>,
Borislav Petkov <bp@...e.de>,
Dan Williams <dan.j.williams@...el.com>,
Dave Hansen <dave.hansen@...el.com>,
David Woodhouse <dwmw@...zon.co.uk>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"H . Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...hat.com>,
Janakarajan Natarajan <Janakarajan.Natarajan@....com>,
Joerg Roedel <joro@...tes.org>,
Jun Nakajima <jun.nakajima@...el.com>,
Laura Abbott <labbott@...hat.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Masami Hiramatsu <mhiramat@...nel.org>,
Paolo Bonzini <pbonzini@...hat.com>,
Peter Zijlstra <peterz@...radead.org>,
Radim Krčmář <rkrcmar@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Tim Chen <tim.c.chen@...ux.intel.com>, kvm@...r.kernel.org,
x86@...nel.org, Arjan Van De Ven <arjan.van.de.ven@...el.com>
Subject: Re: [RFC 09/10] x86/enter: Create macros to restrict/unrestrict
Indirect Branch Speculation
On 1/21/2018 1:14 PM, Andy Lutomirski wrote:
>
>
>> On Jan 20, 2018, at 11:23 AM, KarimAllah Ahmed <karahmed@...zon.de> wrote:
>>
>> From: Tim Chen <tim.c.chen@...ux.intel.com>
>>
>> Create macros to control Indirect Branch Speculation.
>>
>> Name them so they reflect what they are actually doing.
>> The macros are used to restrict and unrestrict the indirect branch speculation.
>> They do not *disable* (or *enable*) indirect branch speculation. A trip back to
>> user-space after *restricting* speculation would still affect the BTB.
>>
>> Quoting from a commit by Tim Chen:
>>
>> """
>> If IBRS is set, near returns and near indirect jumps/calls will not allow
>> their predicted target address to be controlled by code that executed in a
>> less privileged prediction mode *BEFORE* the IBRS mode was last written with
>> a value of 1 or on another logical processor so long as all Return Stack
>> Buffer (RSB) entries from the previous less privileged prediction mode are
>> overwritten.
>>
>> Thus a near indirect jump/call/return may be affected by code in a less
>> privileged prediction mode that executed *AFTER* IBRS mode was last written
>> with a value of 1.
>> """
>>
>> [ tglx: Changed macro names and rewrote changelog ]
>> [ karahmed: changed macro names *again* and rewrote changelog ]
>>
>> Signed-off-by: Tim Chen <tim.c.chen@...ux.intel.com>
>> Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
>> Signed-off-by: KarimAllah Ahmed <karahmed@...zon.de>
>> Cc: Andrea Arcangeli <aarcange@...hat.com>
>> Cc: Andi Kleen <ak@...ux.intel.com>
>> Cc: Peter Zijlstra <peterz@...radead.org>
>> Cc: Greg KH <gregkh@...uxfoundation.org>
>> Cc: Dave Hansen <dave.hansen@...el.com>
>> Cc: Andy Lutomirski <luto@...nel.org>
>> Cc: Paolo Bonzini <pbonzini@...hat.com>
>> Cc: Dan Williams <dan.j.williams@...el.com>
>> Cc: Arjan Van De Ven <arjan.van.de.ven@...el.com>
>> Cc: Linus Torvalds <torvalds@...ux-foundation.org>
>> Cc: David Woodhouse <dwmw@...zon.co.uk>
>> Cc: Ashok Raj <ashok.raj@...el.com>
>> Link: https://lkml.kernel.org/r/3aab341725ee6a9aafd3141387453b45d788d61a.1515542293.git.tim.c.chen@linux.intel.com
>> Signed-off-by: David Woodhouse <dwmw@...zon.co.uk>
>> ---
>> arch/x86/entry/calling.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
>> index 3f48f69..5aafb51 100644
>> --- a/arch/x86/entry/calling.h
>> +++ b/arch/x86/entry/calling.h
>> @@ -6,6 +6,8 @@
>> #include <asm/percpu.h>
>> #include <asm/asm-offsets.h>
>> #include <asm/processor-flags.h>
>> +#include <asm/msr-index.h>
>> +#include <asm/cpufeatures.h>
>>
>> /*
>>
>> @@ -349,3 +351,74 @@ For 32-bit we have the following conventions - kernel is built with
>> .Lafter_call_\@:
>> #endif
>> .endm
>> +
>> +/*
>> + * IBRS related macros
>> + */
>> +.macro PUSH_MSR_REGS
>> + pushq %rax
>> + pushq %rcx
>> + pushq %rdx
>> +.endm
>> +
>> +.macro POP_MSR_REGS
>> + popq %rdx
>> + popq %rcx
>> + popq %rax
>> +.endm
>> +
>> +.macro WRMSR_ASM msr_nr:req edx_val:req eax_val:req
>> + movl \msr_nr, %ecx
>> + movl \edx_val, %edx
>> + movl \eax_val, %eax
>> + wrmsr
>> +.endm
>> +
>> +.macro RESTRICT_IB_SPEC
>> + ALTERNATIVE "jmp .Lskip_\@", "", X86_FEATURE_IBRS
>> + PUSH_MSR_REGS
>> + WRMSR_ASM $MSR_IA32_SPEC_CTRL, $0, $SPEC_CTRL_IBRS
>> + POP_MSR_REGS
>> +.Lskip_\@:
>> +.endm
>> +
>> +.macro UNRESTRICT_IB_SPEC
>> + ALTERNATIVE "jmp .Lskip_\@", "", X86_FEATURE_IBRS
>> + PUSH_MSR_REGS
>> + WRMSR_ASM $MSR_IA32_SPEC_CTRL, $0, $0
>
> I think you should be writing 2, not 0, since I'm reasonably confident that we want STIBP on. Can you explain why you're writing 0?
Do we want to talk about STIBP in general? Should it be (yet another)
boot option to enable or disable? If there is STIBP support without
IBRS support, it could be a set and forget at boot time.
Thanks,
Tom
>
> Also, holy cow, there are so many macros here.
>
> And a meta question: why are there so many submitters of the same series?
>
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