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Message-ID: <20180123181201.GO7844@tassilo.jf.intel.com>
Date: Tue, 23 Jan 2018 10:12:01 -0800
From: Andi Kleen <ak@...ux.intel.com>
To: David Woodhouse <dwmw@...zon.co.uk>
Cc: arjan@...ux.intel.com, tglx@...utronix.de, karahmed@...zon.de,
x86@...nel.org, linux-kernel@...r.kernel.org,
tim.c.chen@...ux.intel.com, bp@...en8.de, peterz@...radead.org,
pbonzini@...hat.com, torvalds@...ux-foundation.org,
gregkh@...ux-foundation.org, thomas.lendacky@....com
Subject: Re: [PATCH v2 5/5] x86/pti: Do not enable PTI on fixed Intel
processors
>
> - if (c->x86_vendor != X86_VENDOR_AMD)
> - setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
> + if (c->x86_vendor != X86_VENDOR_AMD) {
> + u64 ia32_cap = 0;
> +
> + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
> + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
> + if (!(ia32_cap & ARCH_CAP_RDCL_NO))
> + setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
This means that in a hypervisor which passes through the CPUID,
but actually doesn't implement the MSR (so rdmsr #GPs and returns 0)
it would be cleared.
It would be better to usr rdmsrl_safe and check the return value.
-Andi
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