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Message-Id: <1516758426-8127-5-git-send-email-f.fainelli@gmail.com>
Date: Tue, 23 Jan 2018 17:47:04 -0800
From: Florian Fainelli <f.fainelli@...il.com>
To: linux-mips@...ux-mips.org
Cc: Florian Fainelli <florian.fainelli@...adcom.com>,
Florian Fainelli <f.fainelli@...il.com>,
Ralf Baechle <ralf@...ux-mips.org>,
Kevin Cernekee <cernekee@...il.com>,
James Hogan <jhogan@...nel.org>,
Paul Burton <paul.burton@...s.com>,
Matt Redfearn <matt.redfearn@...s.com>,
"Maciej W. Rozycki" <macro@...s.com>,
Huacai Chen <chenhc@...ote.com>,
Kate Stewart <kstewart@...uxfoundation.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Marcin Nowakowski <marcin.nowakowski@...s.com>,
Andrew Morton <akpm@...ux-foundation.org>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
Ingo Molnar <mingo@...nel.org>,
David Howells <dhowells@...hat.com>,
Kees Cook <keescook@...omium.org>,
Thomas Meyer <thomas@...3r.de>,
"Bryan O'Donoghue" <pure.logic@...us-software.ie>,
Robin Murphy <robin.murphy@....com>,
Michal Hocko <mhocko@...e.com>,
Lucas Stach <l.stach@...gutronix.de>,
Vladimir Murzin <vladimir.murzin@....com>,
Bart Van Assche <bart.vanassche@...disk.com>,
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH RFC 4/6] MIPS: Prepare for supporting eXtended KSEG0/1
From: Florian Fainelli <florian.fainelli@...adcom.com>
Prepare the core MIPS files to support Broadcom's eXtended KSEG0/1:
- add MIPS_CPU_XKS01 feature flag
- flag BMIPS4380/5000/5200 with MIPS_CPU_XKS01
- update ioremap and CAC_ADDR() checks
Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
arch/mips/include/asm/cpu-features.h | 8 ++++++++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/include/asm/io.h | 18 ++++++++++--------
arch/mips/include/asm/page.h | 4 ++++
arch/mips/kernel/cpu-probe.c | 3 ++-
arch/mips/mm/ioremap.c | 16 +++++++++-------
6 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 721b698bfe3c..43e1163921a9 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -623,4 +623,12 @@
#define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
#endif
+#if defined(CONFIG_XKS01)
+#ifndef cpu_has_xks01
+# define cpu_has_xks01 (cpu_data[0].options & MIPS_CPU_XKS01)
+#endif
+#else
+# define cpu_has_xks01 0
+#endif /* CONFIG_XKS01 */
+
#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d39324c4adf1..298356b9f7e6 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -418,6 +418,7 @@ enum cpu_type_enum {
MBIT_ULL(54) /* CPU shares FTLB RAM with another */
#define MIPS_CPU_SHARED_FTLB_ENTRIES \
MBIT_ULL(55) /* CPU shares FTLB entries with another */
+#define MIPS_CPU_XKS01 MBIT_ULL(56) /* CPU has eXtended KSEG0/1 */
/*
* CPU ASE encodings
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 0cbf3af37eca..9f4ac0c394be 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -206,14 +206,16 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si
if (!size || last_addr < phys_addr)
return NULL;
- /*
- * Map uncached objects in the low 512MB of address
- * space using KSEG1.
- */
- if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
- flags == _CACHE_UNCACHED)
- return (void __iomem *)
- (unsigned long)CKSEG1ADDR(phys_addr);
+ if (likely(!cpu_has_xks01)) {
+ /*
+ * Map uncached objects in the low 512MB of address
+ * space using KSEG1.
+ */
+ if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
+ flags == _CACHE_UNCACHED)
+ return (void __iomem *)
+ (unsigned long)CKSEG1ADDR(phys_addr);
+ }
}
return __ioremap(offset, size, flags);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index ad461216b5a1..7b8eea14b80e 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -252,8 +252,12 @@ extern int __virt_addr_valid(const volatile void *kaddr);
((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+#ifdef CONFIG_XKS01
+#define CAC_ADDR(addr) ({ BUG(); NULL; })
+#else
#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
+#endif
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index cf3fd549e16d..200087ce9963 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1760,6 +1760,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Broadcom BMIPS4380";
set_elf_platform(cpu, "bmips4380");
c->options |= MIPS_CPU_RIXI;
+ c->options |= MIPS_CPU_XKS01;
} else {
c->cputype = CPU_BMIPS4350;
__cpu_name[cpu] = "Broadcom BMIPS4350";
@@ -1775,7 +1776,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
else
__cpu_name[cpu] = "Broadcom BMIPS5000";
set_elf_platform(cpu, "bmips5000");
- c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
+ c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI | MIPS_CPU_XKS01;
break;
}
}
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 1986e09fb457..f8fd14188909 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -128,13 +128,15 @@ void __iomem * __ioremap(phys_addr_t phys_addr, phys_addr_t size, unsigned long
if (!size || last_addr < phys_addr)
return NULL;
- /*
- * Map uncached objects in the low 512mb of address space using KSEG1,
- * otherwise map using page tables.
- */
- if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
- flags == _CACHE_UNCACHED)
- return (void __iomem *) CKSEG1ADDR(phys_addr);
+ if (likely(!cpu_has_xks01)) {
+ /*
+ * Map uncached objects in the low 512mb of address space using
+ * KSEG1, otherwise map using page tables.
+ */
+ if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
+ flags == _CACHE_UNCACHED)
+ return (void __iomem *) CKSEG1ADDR(phys_addr);
+ }
/*
* Don't allow anybody to remap normal RAM that we're using..
--
2.7.4
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