linux-kernel - [tip:x86/timers] x86/centaur: Mark TSC invariant

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <tip-fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d@git.kernel.org>
Date:   Wed, 24 Jan 2018 04:43:03 -0800
From:   tip-bot for davidwang <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, mingo@...nel.org, hpa@...or.com,
        linux-kernel@...r.kernel.org, davidwang@...oxin.com
Subject: [tip:x86/timers] x86/centaur: Mark TSC invariant

Commit-ID:  fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d
Gitweb:     https://git.kernel.org/tip/fe6daab1ee9dfe7f89974ee6c486cccb0f18a61d
Author:     davidwang <davidwang@...oxin.com>
AuthorDate: Mon, 22 Jan 2018 18:14:17 +0800
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Wed, 24 Jan 2018 13:38:10 +0100

x86/centaur: Mark TSC invariant

Centaur CPU has a constant frequency TSC and that TSC does not stop in
C-States. But because the corresponding TSC feature flags are not set for
that CPU, the TSC is treated as not constant frequency and assumed to stop
in C-States, which makes it an unreliable and unusable clock source.

Setting those flags tells the kernel that the TSC is usable, so it will
select it over HPET.  The effect of this is that reading time stamps (from
kernel or user space) will be faster and more efficent.

Signed-off-by: davidwang <davidwang@...oxin.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: qiyuanwang@...oxin.com
Cc: linux-pm@...r.kernel.org
Cc: brucechang@...-alliance.com
Cc: cooperyan@...oxin.com
Cc: benjaminpan@...tech.com
Link: https://lkml.kernel.org/r/1516616057-5158-1-git-send-email-davidwang@zhaoxin.com

---
 arch/x86/kernel/cpu/centaur.c | 4 ++++
 drivers/acpi/processor_idle.c | 1 +
 2 files changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 68bc6d9..c578cd2 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -106,6 +106,10 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_64
 	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 #endif
+	if (c->x86_power & (1 << 8)) {
+		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+	}
 }
 
 static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index d50a7b6..5f0071c 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -207,6 +207,7 @@ static void tsc_check_state(int state)
 	switch (boot_cpu_data.x86_vendor) {
 	case X86_VENDOR_AMD:
 	case X86_VENDOR_INTEL:
+	case X86_VENDOR_CENTAUR:
 		/*
 		 * AMD Fam10h TSC will tick in all
 		 * C/P/S0/S1 states when this bit is set.