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[198.145.29.99]) by gmr-mx.google.com with ESMTPS id q187si111650iof.3.2018.01.16.01.43.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jan 2018 01:43:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of srs0=1ozf=el=gmail.com=ckoenig.leichtzumerken@kernel.org designates 198.145.29.99 as permitted sender) client-ip=198.145.29.99; Received: by mail.kernel.org (Postfix) id F3EEC2175A; Tue, 16 Jan 2018 09:43:22 +0000 (UTC) Delivered-To: helgaas@kernel.org Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A20A321721 for ; Tue, 16 Jan 2018 09:43:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A20A321721 Received: by mail-wr0-f195.google.com with SMTP id x1so10325307wrb.5 for ; Tue, 16 Jan 2018 01:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:mime-version :content-transfer-encoding; bh=hzppptlGn4tFqrDkRYJ7RoxFLJJVXjwSj9hteosYOpE=; b=GVGDOSc+JQLxWxVzoyB0Erz0hb/roWLx03Ux9WXjwcMH6aBMxJFMKYlaSpV9dtGyON ffvNQQ6QQzg98Hb+ECLtVQSP/Q1VsVd6x0+rYBZSPRch7/J9/vhIj13r6Mpda7wEG9aZ ze7oBWbOtE1NzjuEoz4KOiRXJGBHbpbcJWhQDsrUg+m93nrAg5tKcHQr5AxX50Ju18dq G2XtVFvCuqGgX6NIDO5K+gVm/dQes3TnggIDosk9JQnOM5kqJOzB78ma3nKu6JJz7lax xgE941l4+nUj0Hul8t7nGLKLkkEMxJhHJoV1g77u5Nb7AU8zkZ5qIvnm4Xc/vX+vgdoy nCXw== X-Received: by 10.223.130.196 with SMTP id 62mr21743248wrc.145.1516095800635; Tue, 16 Jan 2018 01:43:20 -0800 (PST) Received: from localhost.localdomain ([2a02:908:1251:8fc0:4055:4d34:fc66:f7ad]) by smtp.gmail.com with ESMTPSA id r5sm2315057wrr.1.2018.01.16.01.43.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jan 2018 01:43:20 -0800 (PST) From: "=?UTF-8?q?Christian=20K=C3=B6nig?=" X-Google-Original-From: =?UTF-8?q?Christian=20K=C3=B6nig?= To: helgaas@kernel.org, bhelgaas@google.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH] x86/PCI: apply the AMD window fixup on resume as well Date: Tue, 16 Jan 2018 10:43:17 +0100 Message-Id: <20180116094317.1603-1-christian.koenig@amd.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-TUID: 0n+tVh75drLh Status: RO X-Status: A Content-Length: 3157 We need to reprogram the register content during resume. Signed-off-by: Christian König Reported-by: Tom St Denis --- arch/x86/pci/fixup.c | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index f6a26e3cb476..8f3b1a6278e6 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -662,11 +662,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid); */ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) { + static const char *name = "PCI Bus 0000:00"; + struct resource *res, *conflict; u32 base, limit, high; struct pci_dev *other; - struct resource *res; unsigned i; - int r; if (!(pci_probe & PCI_BIG_ROOT_WINDOW)) return; @@ -707,21 +707,26 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) * Allocate a 256GB window directly below the 0xfd00000000 hardware * limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6). */ - res->name = "PCI Bus 0000:00"; + res->name = name; res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_WINDOW; res->start = 0xbd00000000ull; res->end = 0xfd00000000ull - 1; - r = request_resource(&iomem_resource, res); - if (r) { + conflict = request_resource_conflict(&iomem_resource, res); + if (conflict) { kfree(res); - return; - } + if (conflict->name != name) + return; - dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n", - res); - add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); + /* We are resuming from suspend, just reprogram the regs. */ + res = conflict; + } else { + dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n", + res); + add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); + pci_bus_add_resource(dev->bus, res, 0); + } base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; @@ -733,13 +738,16 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); - - pci_bus_add_resource(dev->bus, res, 0); } DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); +DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); #endif -- 2.11.0