linux-kernel - Re: [PATCH RFC 1/4] drivers: irqchip: pdc: add support for PDC interrupt controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20180125185236.GD12603@codeaurora.org>
Date:   Thu, 25 Jan 2018 18:52:36 +0000
From:   Lina Iyer <ilina@...eaurora.org>
To:     Marc Zyngier <marc.zyngier@....com>
Cc:     tglx@...utronix.de, jason@...edaemon.net,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        sboyd@...eaurora.org, rnayak@...eaurora.org,
        asathyak@...eaurora.org
Subject: Re: [PATCH RFC 1/4] drivers: irqchip: pdc: add support for PDC
 interrupt controller

Hi Marc,
On Wed, Jan 24 2018 at 14:20 +0000, Marc Zyngier wrote:
>Hi Lina, Archana,
>
>On 23/01/18 17:56, Lina Iyer wrote:
>> From : Archana Sathyakumar <asathyak@...eaurora.org>
>>
>> The Power Domain Controller (PDC) hardware block on Qualcomm SoCs houses
>> an interrupt controller along with other domain control functions to
>> handle interrupt related functions like handle falling edge or active
>> low which are not detected at the GIC and handle wakeup interrupts.
>>
>> The interrupt controller is on an always-on domain for the purpose of
>> waking up the processor, but only a subset of the processor's interrupts
>> are routed through the PDC to the GIC. The PDC powers on the processor's
>> domain, bringing the domain out of low power mode and replays the
>> pending interrupts so the GIC may wake up the processor.
>>
>> Signed-off-by: Archana Sathyakumar <asathyak@...eaurora.org>
>> Signed-off-by: Lina Iyer <ilina@...eaurora.org>
>> [Lina: Split out DT bindings target data and initialization changes]
>> ---

>There is one thing that worries me in this driver. You say that the PDC
>"replays the pending interrupts so the GIC may wake up the processor".
>How is that done without any PM hook allowing for a switch from GIC to
>PDC? How do you ensure that you transition from one to the other without
>loosing interrupts (edge interrupts, in particular)? Or can you get
>spurious interrupts instead?
>
The hand-off between PDC and GIC happens in hardware and is transparent
to software. S/W just enables the PDC pins that would wake up the
processor and when any of those interrupts fire, the hardware powers up
the domain which inturn makes the GIC operational. The PDC then replays
the interrupts so the GIC may see them and wake up the CPUs.

-- Lina