linux-kernel - [tip:x86/pti] x86/cpufeatures: Add Intel feature bits for Speculation Control

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Message-ID: <tip-fc67dd70adb711a45d2ef34e12d1a8be75edde61@git.kernel.org>
Date:   Fri, 26 Jan 2018 07:00:04 -0800
From:   tip-bot for David Woodhouse <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, gregkh@...uxfoundation.org,
        mingo@...nel.org, tglx@...utronix.de, hpa@...or.com, bp@...e.de,
        dwmw@...zon.co.uk
Subject: [tip:x86/pti] x86/cpufeatures: Add Intel feature bits for
 Speculation Control

Commit-ID:  fc67dd70adb711a45d2ef34e12d1a8be75edde61
Gitweb:     https://git.kernel.org/tip/fc67dd70adb711a45d2ef34e12d1a8be75edde61
Author:     David Woodhouse <dwmw@...zon.co.uk>
AuthorDate: Thu, 25 Jan 2018 16:14:10 +0000
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Fri, 26 Jan 2018 15:53:16 +0100

x86/cpufeatures: Add Intel feature bits for Speculation Control

Add three feature bits exposed by new microcode on Intel CPUs for
speculation control.

Signed-off-by: David Woodhouse <dwmw@...zon.co.uk>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Reviewed-by: Borislav Petkov <bp@...e.de>
Cc: gnomes@...rguk.ukuu.org.uk
Cc: ak@...ux.intel.com
Cc: ashok.raj@...el.com
Cc: dave.hansen@...el.com
Cc: karahmed@...zon.de
Cc: arjan@...ux.intel.com
Cc: torvalds@...ux-foundation.org
Cc: peterz@...radead.org
Cc: bp@...en8.de
Cc: pbonzini@...hat.com
Cc: tim.c.chen@...ux.intel.com
Cc: gregkh@...ux-foundation.org
Link: https://lkml.kernel.org/r/1516896855-7642-3-git-send-email-dwmw@amazon.co.uk

---
 arch/x86/include/asm/cpufeatures.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 7b25cf3..0a51070 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -320,6 +320,9 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* Speculation Control (IBRS + IBPB) */
+#define X86_FEATURE_STIBP		(18*32+27) /* Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
 
 /*
  * BUG word(s)