linux-kernel - [tip:perf/core] perf vendor events intel: Update Silvermont events to V14

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Message-ID: <tip-ffaa6f274201cb40721f85a143f6bbd6fc8ef601@git.kernel.org>
Date:   Sun, 28 Jan 2018 13:13:26 -0800
From:   tip-bot for Andi Kleen <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     mingo@...nel.org, hpa@...or.com, acme@...hat.com,
        tglx@...utronix.de, ak@...ux.intel.com,
        linux-kernel@...r.kernel.org
Subject: [tip:perf/core] perf vendor events intel: Update Silvermont events
 to V14

Commit-ID:  ffaa6f274201cb40721f85a143f6bbd6fc8ef601
Gitweb:     https://git.kernel.org/tip/ffaa6f274201cb40721f85a143f6bbd6fc8ef601
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Thu, 18 Jan 2018 04:52:48 -0800
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Thu, 25 Jan 2018 06:37:02 -0300

perf vendor events intel: Update Silvermont events to V14

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 tools/perf/pmu-events/arch/x86/silvermont/cache.json | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
index 0bd1bc5..82be7d1 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
@@ -36,12 +36,13 @@
         "BriefDescription": "L2 cache request misses"
     },
     {
+        "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss.  Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes.  This will include cycles due to an ITLB miss, ICache miss and other events. \r\n",
         "EventCode": "0x86",
         "Counter": "0,1",
         "UMask": "0x4",
         "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
         "SampleAfterValue": "200003",
-        "BriefDescription": "Counts the number of cycles the NIP stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses."
+        "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
     },
     {
         "PEBS": "1",