lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:   Sun, 28 Jan 2018 16:39:48 -0800 (PST)
From:   Liran Alon <liran.alon@...cle.com>
To:     <dwmw2@...radead.org>
Cc:     <konrad.wilk@...cle.com>, <luto@...nel.org>, <tglx@...utronix.de>,
        <torvalds@...ux-foundation.org>, <gregkh@...uxfoundation.org>,
        <asit.k.mallick@...el.com>, <dave.hansen@...el.com>,
        <karahmed@...zon.de>, <jun.nakajima@...el.com>,
        <dan.j.williams@...el.com>, <ashok.raj@...el.com>,
        <daniel.kiper@...cle.com>, <arjan.van.de.ven@...el.com>,
        <tim.c.chen@...ux.intel.com>, <pbonzini@...hat.com>,
        <linux-kernel@...r.kernel.org>, <ak@...ux.intel.com>,
        <kvm@...r.kernel.org>, <aarcange@...hat.com>
Subject: Re: [PATCH] x86: vmx: Allow direct access to MSR_IA32_SPEC_CTRL


----- dwmw2@...radead.org wrote:

> On Sun, 2018-01-28 at 15:21 -0500, Konrad Rzeszutek Wilk wrote:
> > >To avoid the overhead of atomically saving and restoring the
> MSR_IA32_SPEC_CTRL
> > >for guests that do not actually use the MSR, only
> add_atomic_switch_msr when a
> > >non-zero is written to it.
> > 
> > 
> > We tried this and found that it was about 3% slower that doing the
> > old way of rdmsr and wrmsr.
> > 
> > But that was also with the host doing IBRSĀ  as well.
> 
> The common case will be that neither host nor guest are doing IBRS.
> Until the guest touches the MSR we do absolutely *nothing* with it,
> which is definitely the fastest option.

Windows use IBRS and Microsoft don't have any plans to switch to retpoline.
Running a Windows guest should be a pretty common use-case no?

In addition, your handle of the first WRMSR intercept could be different.
It could signal you to start doing the following:
1. Disable intercept on SPEC_CTRL MSR.
2. On VMEntry, Write vCPU SPEC_CTRL value into physical MSR.
3. On VMExit, read physical MSR into vCPU SPEC_CTRL value.
(And if IBRS is used at host, also set physical SPEC_CTRL MSR here to 1)

That way, you will both have fastest option as long as guest don't use IBRS
and also won't have the 3% performance hit compared to Konrad's proposal.

Am I missing something?

-Liran

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ