| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <87b28856-c477-283f-695c-daed42b31287@amazon.com>
Date: Tue, 30 Jan 2018 01:25:07 +0100
From: KarimAllah Ahmed <karahmed@...zon.com>
To: "Raj, Ashok" <ashok.raj@...el.com>,
KarimAllah Ahmed <karahmed@...zon.de>
CC: <kvm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<x86@...nel.org>, Asit Mallick <asit.k.mallick@...el.com>,
Dave Hansen <dave.hansen@...el.com>,
Arjan Van De Ven <arjan.van.de.ven@...el.com>,
Tim Chen <tim.c.chen@...ux.intel.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Andrea Arcangeli <aarcange@...hat.com>,
Andi Kleen <ak@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
Dan Williams <dan.j.williams@...el.com>,
Jun Nakajima <jun.nakajima@...el.com>,
"Andy Lutomirski" <luto@...nel.org>,
Greg KH <gregkh@...uxfoundation.org>,
"Paolo Bonzini" <pbonzini@...hat.com>,
David Woodhouse <dwmw@...zon.co.uk>
Subject: Re: [PATCH v3 3/4] KVM: VMX: Emulate MSR_IA32_ARCH_CAPABILITIES
On 01/30/2018 01:22 AM, Raj, Ashok wrote:
> On Tue, Jan 30, 2018 at 01:10:27AM +0100, KarimAllah Ahmed wrote:
>> Future intel processors will use MSR_IA32_ARCH_CAPABILITIES MSR to indicate
>> RDCL_NO (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default
>> the contents will come directly from the hardware, but user-space can still
>> override it.
>>
>> [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional]
>>
>> Cc: Asit Mallick <asit.k.mallick@...el.com>
>> Cc: Dave Hansen <dave.hansen@...el.com>
>> Cc: Arjan Van De Ven <arjan.van.de.ven@...el.com>
>> Cc: Tim Chen <tim.c.chen@...ux.intel.com>
>> Cc: Linus Torvalds <torvalds@...ux-foundation.org>
>> Cc: Andrea Arcangeli <aarcange@...hat.com>
>> Cc: Andi Kleen <ak@...ux.intel.com>
>> Cc: Thomas Gleixner <tglx@...utronix.de>
>> Cc: Dan Williams <dan.j.williams@...el.com>
>> Cc: Jun Nakajima <jun.nakajima@...el.com>
>> Cc: Andy Lutomirski <luto@...nel.org>
>> Cc: Greg KH <gregkh@...uxfoundation.org>
>> Cc: Paolo Bonzini <pbonzini@...hat.com>
>> Cc: Ashok Raj <ashok.raj@...el.com>
>> Signed-off-by: KarimAllah Ahmed <karahmed@...zon.de>
>> Signed-off-by: David Woodhouse <dwmw@...zon.co.uk>
>> ---
>> arch/x86/kvm/cpuid.c | 2 +-
>> arch/x86/kvm/vmx.c | 15 +++++++++++++++
>> arch/x86/kvm/x86.c | 1 +
>> 3 files changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 033004d..1909635 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -394,7 +394,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
>>
>> /* cpuid 7.0.edx*/
>> const u32 kvm_cpuid_7_0_edx_x86_features =
>> - F(AVX512_4VNNIW) | F(AVX512_4FMAPS);
>> + F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(ARCH_CAPABILITIES);
>>
>> /* all calls to cpuid_count() should be made on the same cpu */
>> get_cpu();
>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>> index ea278ce..798a00b 100644
>> --- a/arch/x86/kvm/vmx.c
>> +++ b/arch/x86/kvm/vmx.c
>> @@ -581,6 +581,8 @@ struct vcpu_vmx {
>> u64 msr_host_kernel_gs_base;
>> u64 msr_guest_kernel_gs_base;
>> #endif
>> + u64 arch_capabilities;
>> +
>> u32 vm_entry_controls_shadow;
>> u32 vm_exit_controls_shadow;
>> u32 secondary_exec_control;
>> @@ -3224,6 +3226,12 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>> case MSR_IA32_TSC:
>> msr_info->data = guest_read_tsc(vcpu);
>> break;
>> + case MSR_IA32_ARCH_CAPABILITIES:
>> + if (!msr_info->host_initiated &&
>> + !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
>> + return 1;
>> + msr_info->data = to_vmx(vcpu)->arch_capabilities;
>> + break;
>> case MSR_IA32_SYSENTER_CS:
>> msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
>> break;
>> @@ -3339,6 +3347,11 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>> if (data & PRED_CMD_IBPB)
>> wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
>> break;
>> + case MSR_IA32_ARCH_CAPABILITIES:
>> + if (!msr_info->host_initiated)
>> + return 1;
>> + vmx->arch_capabilities = data;
>> + break;
>
> arch capabilities is read only. You don't need the set_msr handling for this.
This is only for host driven writes. This would allow QEMU/whatever to
override the default value (i.e. the value from the hardware).
>
>> case MSR_IA32_CR_PAT:
>> if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
>> if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
>> @@ -5599,6 +5612,8 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
>> ++vmx->nmsrs;
>> }
>>
>> + if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
>> + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
>>
>> vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
>>
>> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
>> index 03869eb..8e889dc 100644
>> --- a/arch/x86/kvm/x86.c
>> +++ b/arch/x86/kvm/x86.c
>> @@ -1006,6 +1006,7 @@ static u32 msrs_to_save[] = {
>> #endif
>> MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
>> MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
>> + MSR_IA32_ARCH_CAPABILITIES
>
> Same here.. no need to save/restore this.
>
>> };
>>
>> static unsigned num_msrs_to_save;
>> --
>> 2.7.4
>>
>
Amazon Development Center Germany GmbH
Berlin - Dresden - Aachen
main office: Krausenstr. 38, 10117 Berlin
Geschaeftsfuehrer: Dr. Ralf Herbrich, Christian Schlaeger
Ust-ID: DE289237879
Eingetragen am Amtsgericht Charlottenburg HRB 149173 B
Powered by blists - more mailing lists