linux-kernel - Re: [PATCH v2 2/5] arm64: dts: mt6797: add pwrap support for mt6797

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Message-ID: <dcb5d00a-2239-b214-70a2-cef2e66570fa@gmail.com>
Date:   Tue, 30 Jan 2018 13:57:12 +0100
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     argus.lin@...iatek.com, Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>
Cc:     Chenglin Xu <chenglin.xu@...iatek.com>,
        Sean Wang <sean.wang@...iatek.com>, wsd_upstream@...iatek.com,
        henryc.chen@...iatek.com, flora.fu@...iatek.com,
        Chen Zhong <chen.zhong@...iatek.com>,
        Christophe Jaillet <christophe.jaillet@...adoo.fr>,
        "shailendra . v" <shailendra.v@...sung.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v2 2/5] arm64: dts: mt6797: add pwrap support for mt6797



On 01/29/2018 10:09 AM, argus.lin@...iatek.com wrote:
> From: Argus Lin <argus.lin@...iatek.com>
> 
> mt6797 is a highly integrated SoCs, and it uses
> mt6351 as Power Management IC.
> We need to add pwrap device to communicate with
> mt6351 by SPI.
> The base address of pwrap is 0x1000d000, and IRQ
> number is 178. It also using fixed 26Mhz clock
> as SPI CLK.
> 
> Signed-off-by: Argus Lin <argus.lin@...iatek.com>
> ---

For the next round, can you put the dts patch at the end of the series. Binding
description should be the first patch, but actual dts(i) inclusion should be the
last one. It's bike shedding I know, but as you need a new series anyway.

Thanks.

>  arch/arm64/boot/dts/mediatek/mt6797.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> index 4beaa71107d7..485546efc9bf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi
> @@ -161,6 +161,20 @@
>  		      <0 0x10220690 0 0x10>;
>  	};
>  
> +	pwrap: pwrap@...0d000 {
> +		compatible = "mediatek,mt6797-pwrap";
> +		reg = <0 0x1000d000 0 0x1000>;
> +		reg-names = "pwrap";
> +		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk26m>, <&clk26m>;
> +		clock-names = "spi", "wrap";
> +
> +		pmic: mt6351 {
> +			compatible = "mediatek,mt6351";
> +			interrupt-controller;
> +		};
> +	};
> +
>  	uart0: serial@...02000 {
>  		compatible = "mediatek,mt6797-uart",
>  			     "mediatek,mt6577-uart";
> -- 
> 2.12.5
> 
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