linux-kernel - Re: [PATCH] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits on Intel

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Message-ID: <20180130131122.s3bs6lbs43go73gj@pd.tnic>
Date:   Tue, 30 Jan 2018 14:11:22 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     David Woodhouse <dwmw2@...radead.org>, arjan@...ux.intel.com,
        karahmed@...zon.de, x86@...nel.org, linux-kernel@...r.kernel.org,
        tim.c.chen@...ux.intel.com, peterz@...radead.org,
        pbonzini@...hat.com, ak@...ux.intel.com,
        torvalds@...ux-foundation.org, gregkh@...ux-foundation.org
Subject: Re: [PATCH] x86/cpuid: Fix up "virtual" IBRS/IBPB/STIBP feature bits
 on Intel

On Tue, Jan 30, 2018 at 01:57:21PM +0100, Thomas Gleixner wrote:
> So much for the theory. That's not going to work. If the boot cpu has the
> feature then the alternatives will have been applied. So even if the flag
> mismatch can be observed when a secondary CPU comes up the outcome will be
> access to a non existing MSR and #GP.

Yes, with mismatched microcode we're f*cked.

So my question is: is there such microcode out there or is this
something theoretical which we want to address?

(.. and adressing this will be ugly, no matter what.)

And if I were able to wish, I'd like to blacklist that microcode in
dracut so that it doesn't come anywhere near my system.

-- 
Regards/Gruss,
    Boris.

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