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Message-Id: <20180130202913.28724-27-thierry.escande@collabora.com>
Date: Tue, 30 Jan 2018 21:28:56 +0100
From: Thierry Escande <thierry.escande@...labora.com>
To: Archit Taneja <architt@...eaurora.org>,
Inki Dae <inki.dae@...sung.com>,
Thierry Reding <thierry.reding@...il.com>,
Sandy Huang <hjc@...k-chips.com>,
Sean Paul <seanpaul@...omium.org>,
David Airlie <airlied@...ux.ie>,
Tomasz Figa <tfiga@...omium.org>,
Enric Balletbo i Serra <enric.balletbo@...labora.com>
Cc: Haixia Shi <hshi@...omium.org>,
Ørjan Eide <orjan.eide@....com>,
Zain Wang <wzz@...k-chips.com>,
Yakir Yang <ykk@...k-chips.com>, Lin Huang <hl@...k-chips.com>,
Douglas Anderson <dianders@...omium.org>,
Mark Yao <mark.yao@...k-chips.com>,
linux-kernel@...r.kernel.org, linux-rockchip@...ts.infradead.org,
dri-devel@...ts.freedesktop.org
Subject: [PATCH v3 26/43] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll
From: zain wang <wzz@...k-chips.com>
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson <dianders@...omium.org>
Signed-off-by: zain wang <wzz@...k-chips.com>
Signed-off-by: Sean Paul <seanpaul@...omium.org>
Signed-off-by: Thierry Escande <thierry.escande@...labora.com>
Reviewed-by: Andrzej Hajda <a.hajda@...sung.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 7b7fd227e1f9..02ab1aaa9993 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -230,16 +230,20 @@ enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
{
u32 reg;
+ u32 mask = DP_PLL_PD;
+ u32 pd_addr = ANALOGIX_DP_PLL_CTL;
- if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
- reg |= DP_PLL_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
- } else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
- reg &= ~DP_PLL_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
+ pd_addr = ANALOGIX_DP_PD;
+ mask = RK_PLL_PD;
}
+
+ reg = readl(dp->reg_base + pd_addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + pd_addr);
}
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
--
2.14.1
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