linux-kernel - Re: [PATCH v2 16/16] arm64: Add ARM_SMCCC_ARCH_WORKAROUND

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Message-ID: <501451b6-cc84-e8d3-b7b6-49a7de953976@arm.com>
Date:   Wed, 31 Jan 2018 15:05:53 +0000
From:   Marc Zyngier <marc.zyngier@....com>
To:     Ard Biesheuvel <ard.biesheuvel@...aro.org>
Cc:     Hanjun Guo <guohanjun@...wei.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        kvmarm <kvmarm@...ts.cs.columbia.edu>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Peter Maydell <peter.maydell@...aro.org>,
        Christoffer Dall <christoffer.dall@...aro.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Mark Rutland <mark.rutland@....com>,
        Robin Murphy <robin.murphy@....com>,
        Jon Masters <jcm@...hat.com>
Subject: Re: [PATCH v2 16/16] arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP
 hardening support

On 31/01/18 14:38, Ard Biesheuvel wrote:
> On 31 January 2018 at 14:35, Ard Biesheuvel <ard.biesheuvel@...aro.org> wrote:
>> On 31 January 2018 at 14:11, Marc Zyngier <marc.zyngier@....com> wrote:
>>> On 31/01/18 13:56, Hanjun Guo wrote:
>>>> Hi Marc,
>>>>
>>>> On 2018/1/30 1:45, Marc Zyngier wrote:
>>>>>  static int enable_psci_bp_hardening(void *data)
>>>>>  {
>>>>>      const struct arm64_cpu_capabilities *entry = data;
>>>>>
>>>>> -    if (psci_ops.get_version)
>>>>> +    if (psci_ops.get_version) {
>>>>> +            if (check_smccc_arch_workaround_1(entry))
>>>>> +                    return 0;
>>>>
>>>> If I'm using the new version SMCCC, the firmware have the choicARM_SMCCC_ARCH_WORKAROUND_1e to decide
>>>> whether this machine needs the workaround, even if the CPU is vulnerable
>>>> for CVE-2017-5715, but..
>>>>
>>>>> +
>>>>>              install_bp_hardening_cb(entry,
>>>>>                                     (bp_hardening_cb_t)psci_ops.get_version,
>>>>>                                     __psci_hyp_bp_inval_start,
>>>>>                                     __psci_hyp_bp_inval_end);
>>>>
>>>> ..the code above seems will enable get_psci_version() for CPU and will
>>>> trap to trust firmware even the new version of firmware didn't say
>>>> we need the workaround, did I understand it correctly?
>>>
>>> Well, you only get there if we've established that your CPU is affected
>>> (it has an entry matching its MIDR with the HARDEN_BRANCH_PREDICTOR
>>> capability), and that entry points to enable_psci_bp_hardening. It is
>>> not the firmware that decides whether we need hardening, but the kernel.
>>> The firmware merely provides a facility to apply the hardening.
>>>
>>>> I'm ask this because some platform will not expose to users to
>>>> take advantage of CVE-2017-5715, and we can use different firmware
>>>> to report we need such workaround or not, then use a single kernel
>>>> image for both vulnerable platforms and no vulnerable ones.
>>>
>>> You cannot have your cake and eat it. If you don't want to workaround
>>> the issue, you can disable the hardening. But asking for the same kernel
>>> to do both depending on what the firmware reports doesn't make much
>>> sense to me.
>>
>> The SMCCC v1.1. document does appear to imply that systems that
>> implement SMCCC v1.1 but don't implement ARM_SMCCC_ARCH_WORKAROUND_1
>> should be assumed to be unaffected.
>>
>> """
>> If the discovery call returns NOT_SUPPORTED:
>> • SMCCC_ARCH_WORKAROUND_1 must not be invoked on any PE in the system, and
>> • none of the PEs in the system require firmware mitigation for CVE-2017-5715.
>> """
>>
>> How to deal with conflicting information in this regard (quirk table
>> vs firmware implementation) is a matter of policy, of course.

Yup. And the current approach fits the spec, I believe. The
PSCI_GET_VERSION band-aid should normally be removed shortly after these
patches hit mainline.

> 
> ... and actually, perhaps it makes sense for the
> SMCCC_ARCH_WORKAROUND_1 check to be completely independent of MIDR
> based errata matching?
> 
> I.e., if SMCCC v1.1 and SMCCC_ARCH_WORKAROUND_1 are both implemented,
> we should probably invoke it even if the MIDR is not known to belong
> to an affected implementation.

This would have an impact on big-little systems, for which there is
often a bunch of unaffected CPUs.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...