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Message-ID: <0575AF4FD06DD142AD198903C74E1CC87A605A97@ORSMSX103.amr.corp.intel.com>
Date: Wed, 31 Jan 2018 18:04:36 +0000
From: "Van De Ven, Arjan" <arjan.van.de.ven@...el.com>
To: Jim Mattson <jmattson@...gle.com>,
Paolo Bonzini <pbonzini@...hat.com>
CC: KarimAllah Ahmed <karahmed@...zon.de>,
the arch/x86 maintainers <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>,
kvm list <kvm@...r.kernel.org>,
"Raj, Ashok" <ashok.raj@...el.com>,
"Mallick, Asit K" <asit.k.mallick@...el.com>,
"Hansen, Dave" <dave.hansen@...el.com>,
Tim Chen <tim.c.chen@...ux.intel.com>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Andrea Arcangeli <aarcange@...hat.com>,
Andi Kleen <ak@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>,
"Williams, Dan J" <dan.j.williams@...el.com>,
"Nakajima, Jun" <jun.nakajima@...el.com>,
"Andy Lutomirski" <luto@...nel.org>,
Greg KH <gregkh@...uxfoundation.org>,
"Peter Zijlstra" <peterz@...radead.org>,
David Woodhouse <dwmw@...zon.co.uk>
Subject: RE: [PATCH v4 2/5] KVM: x86: Add IBPB support
> On Wed, Jan 31, 2018 at 8:55 AM, Paolo Bonzini <pbonzini@...hat.com> wrote:
>
> > In fact this MSR can even be passed down unconditionally, since it needs
> > no save/restore and has no ill performance effect on the sibling
> > hyperthread.
>
> I'm a bit surprised to hear that IBPB has no ill performance impact on
> the sibling hyperthread. On current CPUs, this has to flush the BTB,
> doesn't it? And since the BTB is shared between hyperthreads, doesn't
> the sibling lose all of its branch predictions?
IBPB most definitely (in current implementations) will stop both hyperthreads for
the flush.
IBPB is not a cheap operation on a system level
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