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Message-Id: <C841B1F3-9A76-4D09-88AB-EEC4447DB70F@gmail.com>
Date: Wed, 31 Jan 2018 13:17:36 -0800
From: Nadav Amit <nadav.amit@...il.com>
To: Andy Lutomirski <luto@...nel.org>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>,
the arch/x86 maintainers <x86@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>,
LKML <linux-kernel@...r.kernel.org>,
Peter Zijlstra <peterz@...radead.org>
Subject: Re: [PATCH] x86: Align TLB invalidation info
Andy Lutomirski <luto@...nel.org> wrote:
> On Wed, Jan 31, 2018 at 1:09 PM, Nadav Amit <nadav.amit@...il.com> wrote:
>> Dave Hansen <dave.hansen@...ux.intel.com> wrote:
>>
>>> On 01/31/2018 12:11 PM, Nadav Amit wrote:
>>>> The TLB invalidation info is allocated on the stack, which might cause
>>>> it to be unaligned. Since this information may be transferred to
>>>> different cores for TLB shootdown, this might result in an additional
>>>> cache-line bouncing between the cores.
>>>>
>>>> GCC provides a way to deal with it by using
>>>> __builtin_alloca_with_align(). Use it to avoid the bouncing cache lines.
>>>
>>> It doesn't really *bounce*, though, does it? I don't see any writes on
>>> the remote side. The remote use seems entirely read-only.
>>>
>>> You also don't have to exhaustively test this, but I'd love to see at
>>> least a sanity check with a microbenchmark (or something) that, yes,
>>> this does help *something*. Maybe it makes the remote
>>> flush_tlb_func_common() run faster because it's pulling in fewer lines,
>>> or maybe you can even detect fewer misses in there.
>>
>> I agree that with the whole Meltdown/Spectre entry-cost it might not even be
>> measurable, at least on small ( < 2 sockets) machines. But I do not think it
>> worth profiling. Basically, AFAIK, all the data structures that are used for
>> inter-processor communication by the kernel are aligned, and this is an
>> exception.
>
> This is only going to be measurable at all on NUMA, I suspect.
Yes, I meant <= 2 ...
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