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Message-id: <086b44d2-6556-fa7c-1a5b-01c243bf0682@samsung.com>
Date: Wed, 07 Feb 2018 14:04:18 +0100
From: Sylwester Nawrocki <s.nawrocki@...sung.com>
To: Chanwoo Choi <cw00.choi@...sung.com>
Cc: linux-clk@...r.kernel.org, sboyd@...eaurora.org,
mturquette@...libre.com, linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
b.zolnierkie@...sung.com, m.szyprowski@...sung.com
Subject: Re: [PATCH 1/3] clk: exynos5433: Extend list of available AUD_PLL
output frequencies
On 02/07/2018 12:24 PM, Chanwoo Choi wrote:
> Could you share your equation?
> because your result is a little bit different of my result.
> - my equation : ((mdiv + kdiv/65535) x 24MHz) / (pdiv x POWER(2,sdiv))
It resembles the code from samsung_pll36xx_recalc_rate():
(24 * 10^6 * (M * 2^16 + K)) / (P * 2^S) / 2^16
and a more accurate one
ROUNDDOWN(ROUNDDOWN(24 * 10^6 * (M * 2^16 + K), 0) / ROUNDDOWN(P * 2^S, 0) / 2^16, 0)
Shouldn't you substitute 65535 with 65536?
--
Regards,
Sylwester
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