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Message-ID: <CA+pO-2eiim-6E8VLAV2K3s=pqEv7QcV1f8znLeQWqZh=zKWVVQ@mail.gmail.com>
Date: Wed, 7 Feb 2018 16:31:59 +0000
From: Rolf Neugebauer <rolf.neugebauer@...ker.com>
To: Greg KH <gregkh@...uxfoundation.org>
Cc: Borislav Petkov <bp@...en8.de>,
Jia Zhang <zhang.jia@...ux.alibaba.com>,
Thomas Gleixner <tglx@...utronix.de>,
Tony Luck <tony.luck@...el.com>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: x86/microcode/intel: Division by zero panic in 4.9.79 and 4.4.114
On Wed, Feb 7, 2018 at 2:34 PM, Greg KH <gregkh@...uxfoundation.org> wrote:
> On Tue, Feb 06, 2018 at 03:24:44PM +0100, Borislav Petkov wrote:
>> On Tue, Feb 06, 2018 at 02:09:35PM +0000, Rolf Neugebauer wrote:
>> > The backport of 7e702d17ed1 ("x86/microcode/intel: Extend BDW
>> > late-loading further with LLC size check") to 4.9.79 and 4.4.14 causes
>> > a division by zero panic on some single vCPU machine types on Google
>> > Cloud (e.g. g1-small and n1-standard-1):
>>
>> The microcode loader is not supposed to load in a guest.
>>
>> Greg, I guess you need something like this:
>>
>> a15a753539ec ("x86/microcode/AMD: Do not load when running on a hypervisor")
>>
>> I haven't tried whether it applies cleanly though...
>
> It applied cleanly to 4.9 (with some fuzz, but looks clean enough...)
>
> But for 4.4, not at all. Rolf, any chance you could backport the patch
> there for this issue? If not, I can add it to my queue, but it might
> take a few days...
The backport was straight forward. I've added it below. If my mailer
(gmail) screws this up let me where I should send it with 'git
send-email'
Rolf
>From 2cca500deea6a2f47dc126bfe3713933d7192c33 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@...e.de>
Date: Sun, 18 Dec 2016 17:44:13 +0100
Subject: [PATCH 1/1] x86/microcode/AMD: Do not load when running on a
hypervisor
commit a15a753539eca8ba243d576f02e7ca9c4b7d7042 upstream with minor
adjustments.
Doing so is completely void of sense for multiple reasons so prevent
it. Set dis_ucode_ldr to true and thus disable the microcode loader by
default to address xen pv guests which execute the AP path but not the
BSP path.
By having it turned off by default, the APs won't run into the loader
either.
Also, check CPUID(1).ECX[31] which hypervisors set. Well almost, not the
xen pv one. That one gets the aforementioned "fix".
Also, improve the detection method by caching the final decision whether
to continue loading in dis_ucode_ldr and do it once on the BSP. The APs
then simply test that value.
Signed-off-by: Borislav Petkov <bp@...e.de>
Tested-by: Juergen Gross <jgross@...e.com>
Tested-by: Boris Ostrovsky <boris.ostrovsky@...cle.com>
Acked-by: Juergen Gross <jgross@...e.com>
Link: http://lkml.kernel.org/r/20161218164414.9649-4-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: <stable@...r.kernel.org> # 4.4.x
Signed-off-by: Rolf Neugebauer <rolf.neugebauer@...ker.com>
---
arch/x86/kernel/cpu/microcode/core.c | 28 +++++++++++++++++++---------
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/cpu/microcode/core.c
b/arch/x86/kernel/cpu/microcode/core.c
index b3e94ef461fd..1b3e0aa4c511 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -44,7 +44,7 @@
static struct microcode_ops *microcode_ops;
-static bool dis_ucode_ldr;
+static bool dis_ucode_ldr = true;
static int __init disable_loader(char *str)
{
@@ -81,6 +81,7 @@ struct cpu_info_ctx {
static bool __init check_loader_disabled_bsp(void)
{
+ u32 a, b, c, d;
#ifdef CONFIG_X86_32
const char *cmdline = (const char *)__pa_nodebug(boot_command_line);
const char *opt = "dis_ucode_ldr";
@@ -93,8 +94,23 @@ static bool __init check_loader_disabled_bsp(void)
bool *res = &dis_ucode_ldr;
#endif
- if (cmdline_find_option_bool(cmdline, option))
- *res = true;
+ if (!have_cpuid_p())
+ return *res;
+
+ a = 1;
+ c = 0;
+ native_cpuid(&a, &b, &c, &d);
+
+ /*
+ * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not
+ * completely accurate as xen pv guests don't see that CPUID bit set but
+ * that's good enough as they don't land on the BSP path anyway.
+ */
+ if (c & BIT(31))
+ return *res;
+
+ if (cmdline_find_option_bool(cmdline, option) <= 0)
+ *res = false;
return *res;
}
@@ -126,9 +142,6 @@ void __init load_ucode_bsp(void)
if (check_loader_disabled_bsp())
return;
- if (!have_cpuid_p())
- return;
-
vendor = x86_vendor();
family = x86_family();
@@ -162,9 +175,6 @@ void load_ucode_ap(void)
if (check_loader_disabled_ap())
return;
- if (!have_cpuid_p())
- return;
-
vendor = x86_vendor();
family = x86_family();
--
2.16.0
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