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Date:   Thu, 8 Feb 2018 23:32:36 +0100
From:   Sebastian Reichel <sre@...nel.org>
To:     Alexandre Belloni <alexandre.belloni@...e-electrons.com>
Cc:     James Hogan <jhogan@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org,
        linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        devicetree@...r.kernel.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH v3 2/8] dt-bindings: power: reset: Document ocelot-reset
 binding

Hi,

On Tue, Jan 16, 2018 at 11:12:34AM +0100, Alexandre Belloni wrote:
> Add binding documentation for the Microsemi Ocelot reset block.
> 
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: devicetree@...r.kernel.org
> Cc: Sebastian Reichel <sre@...nel.org>
> Cc: linux-pm@...r.kernel.org
> Signed-off-by: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
> ---

Thanks, queued. My public for-next branch is waiting for 4.16-rc1
tag, though.

-- Sebastian

>  .../devicetree/bindings/power/reset/ocelot-reset.txt       | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> new file mode 100644
> index 000000000000..1b4213eb3473
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> @@ -0,0 +1,14 @@
> +Microsemi Ocelot reset controller
> +
> +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
> +SoC MIPS core.
> +
> +Required Properties:
> + - compatible: "mscc,ocelot-chip-reset"
> +
> +Example:
> +	reset@...0008 {
> +		compatible = "mscc,ocelot-chip-reset";
> +		reg = <0x1070008 0x4>;
> +	};
> +
> -- 
> 2.15.1
> 

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