linux-kernel - [RFC PATCH 2/2] KVM: SVM: Add MSR feature support for serializing LFENCE

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Message-ID: <20180208225856.22074.98252.stgit@tlendack-t1.amdoffice.net>
Date:   Thu, 08 Feb 2018 16:58:56 -0600
From:   Tom Lendacky <thomas.lendacky@....com>
To:     x86@...nel.org, linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Cc:     Paolo Bonzini <pbonzini@...hat.com>,
        Joerg Roedel <joro@...tes.org>, Borislav Petkov <bp@...en8.de>,
        Thomas Gleixner <tglx@...utronix.de>,
        Radim Krčmář <rkrcmar@...hat.com>
Subject: [RFC PATCH 2/2] KVM: SVM: Add MSR feature support for serializing
 LFENCE

Create an entry in the new MSR as a feature framework to allow a guest to
recognize LFENCE as a serializing instruction on AMD processors.  The MSR
can only be set by the host, any write by the guest will be ignored.  A
read by the guest will return the value as set by the host.  In this way,
the support to expose the feature to the guest is controlled by the
hypervisor.

Signed-off-by: Tom Lendacky <thomas.lendacky@....com>
---
 arch/x86/kvm/svm.c |   16 ++++++++++++++++
 arch/x86/kvm/x86.c |    6 ++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 1bf20e9..f39e345 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -178,6 +178,8 @@ struct vcpu_svm {
 	uint64_t sysenter_eip;
 	uint64_t tsc_aux;
 
+	u64 msr_decfg;
+
 	u64 next_rip;
 
 	u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
@@ -3912,6 +3914,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			msr_info->data = 0x1E;
 		}
 		break;
+	case MSR_F10H_DECFG:
+		msr_info->data = svm->msr_decfg;
+		break;
 	default:
 		return kvm_get_msr_common(vcpu, msr_info);
 	}
@@ -4047,6 +4052,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
 	case MSR_VM_IGNNE:
 		vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
 		break;
+	case MSR_F10H_DECFG:
+		/* Only the host can set this MSR, silently ignore */
+		if (!msr->host_initiated)
+			break;
+
+		/* Check the supported bits */
+		if (!kvm_valid_msr_feature(MSR_F10H_DECFG, data))
+			return 1;
+
+		svm->msr_decfg = data;
+		break;
 	case MSR_IA32_APICBASE:
 		if (kvm_vcpu_apicv_active(vcpu))
 			avic_update_vapic_bar(to_svm(vcpu), data);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 4251c34..21ec73b 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1060,7 +1060,13 @@ struct kvm_msr_based_features {
 	u64 value;			/* MSR value */
 };
 
+static const struct x86_cpu_id msr_decfg_match[] = {
+	{ X86_VENDOR_AMD, X86_FAMILY_ANY, X86_MODEL_ANY, X86_FEATURE_LFENCE_RDTSC },
+	{}
+};
+
 static struct kvm_msr_based_features msr_based_features[] = {
+	{ MSR_F10H_DECFG, MSR_F10H_DECFG_LFENCE_SERIALIZE, msr_decfg_match },
 	{}
 };