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Message-ID: <CAL_JsqLvkPEm1mZaEfEVFEYMoGvOsbSQb8c35UvjmRTCwrCF8Q@mail.gmail.com>
Date:   Mon, 12 Feb 2018 10:43:41 -0600
From:   Rob Herring <robh@...nel.org>
To:     Enric Balletbo Serra <eballetbo@...il.com>
Cc:     Enric Balletbo i Serra <enric.balletbo@...labora.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Brian Norris <briannorris@...omium.org>,
        Heiko Stuebner <heiko@...ech.de>,
        Doug Anderson <dianders@...omium.org>,
        Chris Zhong <zyw@...k-chips.com>,
        William wu <wulf@...k-chips.com>,
        huang lin <hl@...k-chips.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        kernel@...labora.com
Subject: Re: [PATCH 2/3] Documentation: bindings: add usb3-host-disable and
 usb3-host-port for Rockchip USB Type-C PHY

On Thu, Feb 8, 2018 at 3:23 PM, Enric Balletbo Serra
<eballetbo@...il.com> wrote:
> Hi Rob,
>
> 2018-02-08 18:52 GMT+01:00 Rob Herring <robh@...nel.org>:
>> On Thu, Feb 8, 2018 at 9:20 AM, Enric Balletbo i Serra
>> <enric.balletbo@...labora.com> wrote:
>>> From: William wu <wulf@...k-chips.com>
>>>
>>> rockchip,usb3-host-disable is the register of type-c phy disable usb3 host
>>> rockchip,usb3-host-port is the register of type-c phy usb3 port number
>>>
>>> Signed-off-by: William wu <wulf@...k-chips.com>
>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
>>> ---
>>>  Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>> index c3be83be9615..9085d95d0079 100644
>>> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
>>> @@ -36,6 +36,12 @@ offset, enable bit, write mask bit.
>>>   - rockchip,uphy-dp-sel : the register of type-c phy enable DP function
>>>     for type-c phy0, it must be <0x6268 19 19>;
>>>     for type-c phy1, it must be <0x6268 3 19>;
>>> + - rockchip,usb3-host-disable : the register of type-c phy disable usb3 host
>>> +   for type-c phy0, it must be <0x2434 0 16>;
>>> +   for type-c phy1, it must be <0x2444 0 16>;
>>> + - rockchip,usb3-host-port : the register of type-c phy usb3 port number
>>> +   for type-c phy0, it must be <0x2434 12 28>;
>>> +   for type-c phy1, it must be <0x2444 12 28>;
>>
>> When does this list stop? Adding properties for various register
>> fields doesn't scale. This information should be in the driver and
>> based on the compatible string if necessary.
>>
>
> I see, seams reasonable to me, is this applicable to the new ones only
> or I should get rid of all the proprieties like this from the DT
> (including the old ones)?

We're already kind of stuck with the existing ones. So it depends if
people want to phase them out or not.

Rob

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