linux-kernel - Re: [BUG] x86 : i486 reporting to be vulnerable to Meltdown/Spectre_V1/Spectre

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Message-ID: <20180213234533.368ce82b@alans-desktop>
Date:   Tue, 13 Feb 2018 23:45:33 +0000
From:   Alan Cox <gnomes@...rguk.ukuu.org.uk>
To:     Pavel Machek <pavel@....cz>
Cc:     tedheadster <tedheadster@...il.com>, whiteheadm@....org,
        David Laight <David.Laight@...lab.com>,
        Arnd Bergmann <arnd@...db.de>,
        Ondrej Zary <linux@...nbow-software.org>,
        David Woodhouse <dwmw2@...radead.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Hugh Dickins <hughd@...gle.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Jiri Kosina <jikos@...nel.org>, Borislav Petkov <bp@...en8.de>,
        Kees Cook <keescook@...omium.org>,
        Jamie Iles <jamie@...ieiles.com>,
        Eduardo Valentin <eduval@...zon.com>,
        Laura Abbott <labbott@...hat.com>,
        Rik van Riel <riel@...riel.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [BUG] x86 : i486 reporting to be vulnerable to
 Meltdown/Spectre_V1/Spectre_V2

On Tue, 13 Feb 2018 22:04:48 +0100
Pavel Machek <pavel@....cz> wrote:

> On Thu 2018-02-08 20:52:40, Alan Cox wrote:
> > > > Also worth nothing that the difference between the cpu and memory
> > > > speeds is much lower - so far fewer instructions could be speculatively
> > > > executed while waiting a cache miss.  
> > 
> > But they also have more instructions that take a lot of clocks and are
> > easier to stall - eg by doing things like opening and mmapping
> > a framebuffer and then doing a floating point double store to it
> > misaligned.
> > 
> > Meltdown we can at least reasonably test but spectre is hard.  
> 
> Do you have pointer for simple meltdown test?

It's CPU dependent but for the older processors you probably want one of
the small ones as you've got much less cache and speculation to play with.

And then you also need the test data to be in L1 D cache

Alan