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Message-ID: <f5d6d768-d354-56b5-ce0c-4f46d4e6d642@codeaurora.org>
Date:   Mon, 12 Feb 2018 18:10:38 -0600
From:   Timur Tabi <timur@...eaurora.org>
To:     Florian Fainelli <f.fainelli@...il.com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     tchalamarla@...ium.com, rrichter@...ium.com, opendmb@...il.com,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Mark Rutland <mark.rutland@....com>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] arm64: Make L1_CACHE_SHIFT configurable

On 02/12/2018 05:57 PM, Florian Fainelli wrote:
> That is debatable, is there a good publicly available table of what the
> typical L1 cache line size is on ARMv8 platforms?

I don't have that, but I was under the impression that we moved from 6 
to 7 because more and more ARMv8 platforms have 128-byte caches, so that 
is the "new normal".

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

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