linux-kernel - Re: [PATCH v2] libnvdimm: re-enable deep flush for pmem devices

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Message-ID: <CAPcyv4j7dnmiRxkFr8DgBLd-xkm8vS+T8xmZWSxUgOp8JZPhLQ@mail.gmail.com>
Date:   Tue, 13 Feb 2018 07:57:36 -0800
From:   Dan Williams <dan.j.williams@...el.com>
To:     Jeff Moyer <jmoyer@...hat.com>
Cc:     Dave Jiang <dave.jiang@...el.com>,
        "Zwisler, Ross" <ross.zwisler@...el.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-nvdimm@...ts.01.org
Subject: Re: [PATCH v2] libnvdimm: re-enable deep flush for pmem devices

On Tue, Feb 13, 2018 at 5:17 AM, Jeff Moyer <jmoyer@...hat.com> wrote:
> Dan Williams <dan.j.williams@...el.com> writes:
>
>> On Mon, Feb 12, 2018 at 2:53 PM, Jeff Moyer <jmoyer@...hat.com> wrote:
>>> Dave Jiang <dave.jiang@...el.com> writes:
>>>
>>>> Re-enable deep flush so that users always have a way to be sure that a write
>>>> does make it all the way out to the NVDIMM. The PMEM driver writes always
>>>> make it "all the way to the NVDIMM", and it relies on the ADR mechanism to
>>>> flush the write buffers on power failure. Deep flush is there to explicitly
>>>> flush those write buffers to protect against (rare) ADR failure.
>>>> This change prevents a regression in deep flush behavior so that applications
>>>> can continue to depend on fsync() as a mechanism to trigger deep flush in the
>>>> filesystem-dax case.
>>>
>>> That's still very confusing text.  Specifically, the part where you say
>>> that pmem driver writes always make it to the DIMM.  I think the
>>> changelog could start with "Deep flush is there to explicitly flush
>>> write buffers...."  Anyway, the fix looks right to me.
>>
>> I ended up changing the commit message to this, let me know if it reads better:
>
> Thanks.  It's still unclear to me what the text, "The PMEM driver writes
> always arrive at the NVDIMM" means.  However, it's good enough.

Yeah, Dave, had similar feedback. A better way of saying it is that
the writes always arrive at the persistence domain, but deep flush
pushes them to the smallest platform failure domain. On current
platforms that's to the ADR domain and past the ADR domain.