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Message-ID: <alpine.DEB.2.21.1802131659520.1130@nanos.tec.linutronix.de>
Date: Tue, 13 Feb 2018 17:02:59 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: Andi Kleen <ak@...ux.intel.com>
cc: Arjan van de Ven <arjan@...ux.intel.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Nick Lowe <nick.lowe@...il.com>, linux-kernel@...r.kernel.org,
stable@...r.kernel.org, David Woodhouse <dwmw@...zon.co.uk>,
Borislav Petkov <bp@...e.de>,
Dave Hansen <dave.hansen@...el.com>,
gnomes@...rguk.ukuu.org.uk, ashok.raj@...el.com,
karahmed@...zon.de, torvalds@...ux-foundation.org,
peterz@...radead.org, Borislav Petkov <bp@...en8.de>,
pbonzini@...hat.com, tim.c.chen@...ux.intel.com
Subject: Re: [PATCH 4.9 43/92] x86/pti: Do not enable PTI on CPUs which are
not vulnerable to Meltdown
On Tue, 13 Feb 2018, Andi Kleen wrote:
> On Tue, Feb 13, 2018 at 07:09:44AM -0800, Arjan van de Ven wrote:
> > >
> > > So, any hints on what you think should be the correct fix here?
> >
> > the patch sure looks correct to me, it now has a nice table for CPU IDs
> > including all of AMD (and soon hopefully the existing Intel ones that are not exposed to meltdown)
>
> I don't think the table is nice, it's a white list that would need
> to be maintained forever.
No. The table is basically excluding families <=5 and a few individual
ones. Anything newer than that should tell via ARCH_CAP_RDCL_NO and not
need any entry.
Thanks,
tglx
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