lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Wed, 14 Feb 2018 09:04:12 -0800 From: Florian Fainelli <f.fainelli@...il.com> To: Daniel Schultz <d.schultz@...tec.de>, robh+dt@...nel.org, mark.rutland@....com, andrew@...n.ch, netdev@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org CC: w.egorov@...tec.de Subject: Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option On February 14, 2018 8:07:11 AM PST, Daniel Schultz <d.schultz@...tec.de> wrote: >From: Wadim Egorov <w.egorov@...tec.de> > >The DP83867 has a muxing option for the CLK_OUT pin. It is possible >to set CLK_OUT for different channels. >Create a binding to select a specific clock for CLK_OUT pin. > >Signed-off-by: Wadim Egorov <w.egorov@...tec.de> >Signed-off-by: Daniel Schultz <d.schultz@...tec.de> >--- >Changes: > v2: > Added check if clk_output_sel has a valid value > Only write the clock ouput register if a musing is desired > v3: > - > > drivers/net/phy/dp83867.c | 19 +++++++++++++++++++ > include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++ > 2 files changed, 33 insertions(+) > >diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c >index c1ab976..a862194 100644 >--- a/drivers/net/phy/dp83867.c >+++ b/drivers/net/phy/dp83867.c >@@ -75,6 +75,8 @@ > > #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 > #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f >+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) >+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 > Nit: it looks like you could use the shift constant you define for defining the mask as well. Other than that: Reviewed-by: Florian Fainelli <f.fainelli@...il.com> -- Florian
Powered by blists - more mailing lists