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Message-ID: <1518701697-14242-4-git-send-email-ludovic.Barre@st.com>
Date: Thu, 15 Feb 2018 14:34:55 +0100
From: Ludovic Barre <ludovic.Barre@...com>
To: Ulf Hansson <ulf.hansson@...aro.org>,
Rob Herring <robh+dt@...nel.org>
CC: Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...com>,
Gerald Baeza <gerald.baeza@...com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-mmc@...r.kernel.org>, Ludovic Barre <ludovic.barre@...com>
Subject: [PATCH 3/5] ARM: dts: stm32: add sdmmc support for stm32h743
From: Ludovic Barre <ludovic.barre@...com>
This patch adds sdmmc support for stm32h743.
2×SD/SDIO/MMC interfaces (up to 125 MHz)
Signed-off-by: Ludovic Barre <ludovic.barre@...com>
---
arch/arm/boot/dts/stm32h743.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index bbfcbac..5e85538 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -217,6 +217,19 @@
};
};
+ sdmmc2: sdmmc@...22400 {
+ compatible = "st,stm32h7-sdmmc";
+ reg = <0x48022400 0x400>;
+ reg-names = "sdmmc";
+ interrupts = <124>;
+ clocks = <&rcc SDMMC2_CK>;
+ resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <125000000>;
+ status = "disabled";
+ };
+
mdma1: dma@...00000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
@@ -227,6 +240,19 @@
dma-requests = <32>;
};
+ sdmmc1: sdmmc@...07000 {
+ compatible = "st,stm32h7-sdmmc";
+ reg = <0x52007000 0x1000>;
+ reg-names = "sdmmc";
+ interrupts = <49>;
+ clocks = <&rcc SDMMC1_CK>;
+ resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <125000000>;
+ status = "disabled";
+ };
+
lptimer2: timer@...02400 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4
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