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Message-ID: <20180216201818.j5gunpkkebq35b4n@flea.lan>
Date: Fri, 16 Feb 2018 21:18:18 +0100
From: Maxime Ripard <maxime.ripard@...tlin.com>
To: Giulio Benetti <giulio.benetti@...ronovasrl.com>
Cc: Chen-Yu Tsai <wens@...e.org>, dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] drm/sun4i: fix HSYNC and VSYNC polarity
On Thu, Feb 15, 2018 at 06:54:48PM +0100, Giulio Benetti wrote:
> Differently from other Lcd signals, HSYNC and VSYNC signals
> result inverted if their bits are cleared to 0.
>
> Invert their settings of IO_POL register.
>
> Signed-off-by: Giulio Benetti <giulio.benetti@...ronovasrl.com>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
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