linux-kernel - [tip:locking/core] memory-barriers: Fix description of data dependency barriers

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Date:   Wed, 21 Feb 2018 02:42:53 -0800
From:   tip-bot for Nikolay Borisov <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     mingo@...nel.org, torvalds@...ux-foundation.org,
        linux-kernel@...r.kernel.org, paulmck@...ux.vnet.ibm.com,
        peterz@...radead.org, hpa@...or.com, nborisov@...e.com,
        tglx@...utronix.de
Subject: [tip:locking/core] memory-barriers: Fix description of data
 dependency barriers

Commit-ID:  51de78892b1294d1521c41226a5ef215a910c25f
Gitweb:     https://git.kernel.org/tip/51de78892b1294d1521c41226a5ef215a910c25f
Author:     Nikolay Borisov <nborisov@...e.com>
AuthorDate: Tue, 20 Feb 2018 15:25:08 -0800
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 21 Feb 2018 09:58:14 +0100

memory-barriers: Fix description of data dependency barriers

In the description of data dependency barriers the words 'before' is
used erroneously. Since such barrier order dependent loads one after
the other. So substitute 'before' with 'after'.

Signed-off-by: Nikolay Borisov <nborisov@...e.com>
Signed-off-by: Paul E. McKenney <paulmck@...ux.vnet.ibm.com>
Acked-by: Peter Zijlstra <peterz@...radead.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: akiyks@...il.com
Cc: boqun.feng@...il.com
Cc: dhowells@...hat.com
Cc: j.alglave@....ac.uk
Cc: linux-arch@...r.kernel.org
Cc: luc.maranget@...ia.fr
Cc: npiggin@...il.com
Cc: parri.andrea@...il.com
Cc: stern@...land.harvard.edu
Cc: will.deacon@....com
Link: http://lkml.kernel.org/r/1519169112-20593-8-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 Documentation/memory-barriers.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index a37d3af..da6525b 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -403,7 +403,7 @@ Memory barriers come in four basic varieties:
      where two loads are performed such that the second depends on the result
      of the first (eg: the first load retrieves the address to which the second
      load will be directed), a data dependency barrier would be required to
-     make sure that the target of the second load is updated before the address
+     make sure that the target of the second load is updated after the address
      obtained by the first load is accessed.
 
      A data dependency barrier is a partial ordering on interdependent loads