Message-Id: <20180223210901.23480-2-rasmus.villemoes@prevas.dk>
Date:   Fri, 23 Feb 2018 22:08:59 +0100
From:   Rasmus Villemoes <rasmus.villemoes@...vas.dk>
To:     Rob Herring <robh+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>
Cc:     Andy Tang <andy.tang@....com>,
        Alexander Stein <alexander.stein@...tec-electronic.com>,
        Rasmus Villemoes <rasmus.villemoes@...vas.dk>,
        linux-kernel@...r.kernel.org
Subject: [PATCH v5 1/2] irqchip: add support for Layerscape external interrupt lines

The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.

In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.

Some other Layerscape SOCs (LS1043A, LS1046A) reportedly have a similar
feature, just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node, but I don't have the full reference manual, nor the hardware to be
able to test it. I do know, from a tiny clipout from one of the other
reference manuals I was shown, that 1U<<n is the right formula to
use for setting/clearing the bit corresponding to the external IRQn, but
I don't know which interrupts on the GIC those lines represent.

There's also a little Kconfig/Kbuild issue: For now, I've let the driver
be built if CONFIG_SOC_LS1021A is set. For the others, it might make
sense to instead use CONFIG_ARCH_LAYERSCAPE, but SOC_LS1021A does not
select ARCH_LAYERSCAPE. The simplest solution is probably to do what is
done for irq-ls-scfg-msi.c: introduce a "def_bool y if SOC_LS1021A ||
ARCH_LAYERSCAPE" symbol. But I think that can wait until somebody with
the hardware actually tests that this works for the other platforms. At
that point, one can also add the extra IRQCHIP_DECLARE instances.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@...vas.dk>
---
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-ls-extirq.c | 176 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 177 insertions(+)
 create mode 100644 drivers/irqchip/irq-ls-extirq.c

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d27e3e3619e0..6fe8612e6a49 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_MVEBU_ICU)			+= irq-mvebu-icu.o
 obj-$(CONFIG_MVEBU_ODMI)		+= irq-mvebu-odmi.o
 obj-$(CONFIG_MVEBU_PIC)			+= irq-mvebu-pic.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
+obj-$(CONFIG_SOC_LS1021A)		+= irq-ls-extirq.o
 obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o
 obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
new file mode 100644
index 000000000000..e5665ad867d6
--- /dev/null
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#define pr_fmt(fmt) "irq-ls-extirq: " fmt
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define MAXIRQ 12
+
+struct extirq_chip_data {
+	struct regmap *syscon;
+	u32           intpcr;
+	bool          bit_reverse;
+	u32           nirq;
+	u32           parent_irq[MAXIRQ];
+};
+
+static int
+ls_extirq_set_type(struct irq_data *data, unsigned int type)
+{
+	irq_hw_number_t hwirq = data->hwirq;
+	struct extirq_chip_data *chip_data = data->chip_data;
+	u32 value, mask;
+
+	if (chip_data->bit_reverse)
+		mask = 1U << (31 - hwirq);
+	else
+		mask = 1U << hwirq;
+
+	switch (type) {
+	case IRQ_TYPE_LEVEL_LOW:
+		type = IRQ_TYPE_LEVEL_HIGH;
+		value = mask;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		type = IRQ_TYPE_EDGE_RISING;
+		value = mask;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+	case IRQ_TYPE_EDGE_RISING:
+		value = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_update_bits(chip_data->syscon, chip_data->intpcr, mask, value);
+
+	data = data->parent_data;
+	return data->chip->irq_set_type(data, type);
+}
+
+static struct irq_chip extirq_chip = {
+	.name			= "extirq",
+	.irq_mask		= irq_chip_mask_parent,
+	.irq_unmask		= irq_chip_unmask_parent,
+	.irq_eoi		= irq_chip_eoi_parent,
+	.irq_set_type		= ls_extirq_set_type,
+	.irq_retrigger		= irq_chip_retrigger_hierarchy,
+	.irq_set_affinity	= irq_chip_set_affinity_parent,
+	.flags                  = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static int
+ls_extirq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
+			   unsigned long *hwirq, unsigned int *type)
+{
+	if (!is_of_node(fwspec->fwnode))
+		return -EINVAL;
+
+	if (fwspec->param_count != 2)
+		return -EINVAL;
+
+	*hwirq = fwspec->param[0];
+	*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
+	return 0;
+}
+
+static int
+ls_extirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+		       unsigned int nr_irqs, void *arg)
+{
+	irq_hw_number_t hwirq;
+	struct irq_fwspec *fwspec = arg;
+	struct irq_fwspec gic_fwspec;
+	struct extirq_chip_data *chip_data = domain->host_data;
+
+	if (fwspec->param_count != 2)
+		return -EINVAL;
+
+	hwirq = fwspec->param[0];
+	if (hwirq >= chip_data->nirq)
+		return -EINVAL;
+
+	irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &extirq_chip,
+				      chip_data);
+
+	gic_fwspec.fwnode = domain->parent->fwnode;
+	gic_fwspec.param_count = 3;
+	gic_fwspec.param[0] = GIC_SPI;
+	gic_fwspec.param[1] = chip_data->parent_irq[hwirq];
+	gic_fwspec.param[2] = fwspec->param[1];
+
+	return irq_domain_alloc_irqs_parent(domain, virq, 1, &gic_fwspec);
+}
+
+static const struct irq_domain_ops extirq_domain_ops = {
+	.translate	= ls_extirq_domain_translate,
+	.alloc		= ls_extirq_domain_alloc,
+	.free		= irq_domain_free_irqs_common,
+};
+
+static int __init
+ls_extirq_of_init(struct device_node *node, struct device_node *parent)
+{
+
+	struct irq_domain *domain, *domain_parent;
+	struct extirq_chip_data *chip;
+	const __be32 *intpcr;
+	int ret;
+
+	domain_parent = irq_find_host(parent);
+	if (!domain_parent) {
+		pr_err("interrupt-parent not found\n");
+		return -EINVAL;
+	}
+
+	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->syscon = syscon_node_to_regmap(node->parent);
+	if (IS_ERR(chip->syscon)) {
+		ret = PTR_ERR(chip->syscon);
+		pr_err("Failed to lookup parent regmap\n");
+		goto err;
+	}
+	intpcr = of_get_address(node, 0, NULL, NULL);
+	if (!intpcr) {
+		ret = -ENOENT;
+		pr_err("Missing INTPCR offset value\n");
+		goto err;
+	}
+	chip->intpcr = __be32_to_cpu(*intpcr);
+
+	ret = of_property_read_variable_u32_array(node, "fsl,extirq-map",
+						  chip->parent_irq,
+						  1, ARRAY_SIZE(chip->parent_irq));
+	if (ret < 0)
+		goto err;
+	chip->nirq = ret;
+	chip->bit_reverse = of_property_read_bool(node, "fsl,bit-reverse");
+
+	domain = irq_domain_add_hierarchy(domain_parent, 0, chip->nirq, node,
+					  &extirq_domain_ops, chip);
+	if (!domain) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	return 0;
+
+err:
+	kfree(chip);
+	return ret;
+}
+
+IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
-- 
2.15.1

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