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Message-ID: <0575AF4FD06DD142AD198903C74E1CC87A61DDF7@ORSMSX103.amr.corp.intel.com>
Date:   Fri, 23 Feb 2018 18:18:52 +0000
From:   "Van De Ven, Arjan" <arjan.van.de.ven@...el.com>
To:     Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
        Paolo Bonzini <pbonzini@...hat.com>
CC:     "valdis.kletnieks@...edu" <valdis.kletnieks@...edu>,
        Jon Masters <jcm@...masters.org>,
        David Woodhouse <dwmw2@...radead.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "x86@...nel.org" <x86@...nel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "torvalds@...ux-foundation.org" <torvalds@...ux-foundation.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Hansen, Dave" <dave.hansen@...el.com>,
        Ingo Molnar <mingo@...nel.org>
Subject: RE: RSB Alternative bit in IA32_ARCH_CAPABILITIES Was:Re: [PATCH
 2/2] x86/speculation: Support "Enhanced IBRS" on future CPUs

> To add a bit more to this, Intel just updated their
> IA32_ARCH_CAPABILITIES_MSR
> to have a new bit to sample to figure out whether you need IBRS or not
> during runtime.

actually we updated the document when you need RSB stuffing.
based on the request of various folks here on LKML.

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