linux-kernel - Re: [PATCH v4 4/6] arm64: dts: exynos: add OF graph between MHL and USB connector

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Message-ID: <CAL_JsqKGVwvqu36D57WbB7bPMt2tOZmvq+ukFuNHbhgiWYuw-w@mail.gmail.com>
Date:   Tue, 27 Feb 2018 15:24:34 -0600
From:   Rob Herring <robh+dt@...nel.org>
To:     Andrzej Hajda <a.hajda@...sung.com>
Cc:     "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        Inki Dae <inki.dae@...sung.com>,
        Mark Rutland <mark.rutland@....com>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Archit Taneja <architt@...eaurora.org>,
        Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        linux-samsung-soc@...r.kernel.org,
        Linux USB List <linux-usb@...r.kernel.org>
Subject: Re: [PATCH v4 4/6] arm64: dts: exynos: add OF graph between MHL and
 USB connector

On Wed, Feb 21, 2018 at 2:55 AM, Andrzej Hajda <a.hajda@...sung.com> wrote:
> OF graph describes MHL data lanes between MHL and respective USB
> connector.
>
> Signed-off-by: Andrzej Hajda <a.hajda@...sung.com>
> ---
> v4:
> - added missing reg property in connector's port node (Krzysztof)
> ---
>  .../boot/dts/exynos/exynos5433-tm2-common.dtsi     | 32 ++++++++++++++++++++--
>  1 file changed, 29 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index f604f6b1a9c2..2ed506df94d0 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -817,9 +817,22 @@
>                 clocks = <&pmu_system_controller 0>;
>                 clock-names = "xtal";
>
> -               port {
> -                       mhl_to_hdmi: endpoint {
> -                               remote-endpoint = <&hdmi_to_mhl>;
> +               ports {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       port@0 {
> +                               reg = <0>;
> +                               mhl_to_hdmi: endpoint {
> +                                       remote-endpoint = <&hdmi_to_mhl>;
> +                               };
> +                       };
> +
> +                       port@1 {
> +                               reg = <1>;
> +                               mhl_to_musb_con: endpoint {
> +                                       remote-endpoint = <&musb_con_to_mhl>;
> +                               };

These ports are mutually exclusive, right? If so, it should be 1 port
with 2 endpoints. Ports should represent independent data flows.
Something muxed or replicated (1 to many connection) should be be
endpoints.

Rob